參數(shù)資料
型號: MPC8306CVMACDCA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 200 MHz, RISC PROCESSOR, PBGA369
封裝: 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MAPBGA-369
文件頁數(shù): 4/76頁
文件大?。?/td> 474K
代理商: MPC8306CVMACDCA
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
12
Freescale Semiconductor
Clock Input Timing
4
Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the MPC8306.
NOTE
The rise/fall time on QUICC Engine input pins should not exceed 5 ns. This
should be enforced especially on clock signals. Rise time refers to signal
transitions from 10% to 90% of OVDD; fall time refers to transitions from
90% to 10% of OVDD.
4.1
DC Electrical Characteristics
Table 7 provides the clock input (SYS_CLK_IN) DC specifications for the MPC8306. These
specifications are also applicable for QE_CLK_IN.
4.2
AC Electrical Characteristics
The primary clock source for the MPC8306 is SYS_CLK_IN. Table 8 provides the clock input
(SYS_CLK_IN) AC timing specifications for the MPC8306. These specifications are also applicable for
QE_CLK_IN.
Table 7. SYS_CLK_IN DC Electrical Characteristics
Parameter
Condition
Symbol
Min
Max
Unit
Input high voltage
VIH
2.4
OVDD +0.3
V
Input low voltage
VIL
–0.3
0.4
V
SYS_CLK_IN input current
0 V
VIN OVDD
IIN
—±5
A
SYS_CLK_IN input current
0 V
VIN 0.5 V or
OVDD – 0.5 V VIN OVDD
IIN
—±5
A
SYS_CLK_IN input current
0.5 V
VIN OVDD – 0.5 V
IIN
—±50
A
Table 8. SYS_CLK_IN AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
SYS_CLK_IN frequency
fSYS_CLK_IN
24
66.67
MHz
1
SYS_CLK_IN cycle time
tSYS_CLK_IN
15
41.6
ns
SYS_CLK_IN rise and fall time
tKH, tKL
1.1
2.8
ns
2
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