參數(shù)資料
型號(hào)： MPC8280VVUPEA
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 80/83頁(yè)
文件大?。?/td> 0K
描述： IC MPU POWERQUICC II 480-TBGA
標(biāo)準(zhǔn)包裝： 21
系列： MPC82xx
處理器類(lèi)型： 32-位 MPC82xx PowerQUICC II
速度： 450MHz
電壓： 1.5V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 480-LBGA
供應(yīng)商設(shè)備封裝： 408-TBGA（37.5x37.5）
包裝： 托盤(pán)
MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2
Freescale Semiconductor
81
Document Revision History
1.0
2/2004
Removal of “Advance Information” and “Preliminary.” The MPC8280 is fully qualified.
Table 2: New
Figure 1: Modification to note 2
Section 1.1: Core frequency range is 166–450 MHz
Addition of ZQ (516 PBGA with Lead spheres) package references
Table 4: VDD and VCCSYN modified to 1.45–1.60 V
Note following Table 4: Modified
Table 5: Addition of note 2 regarding TRST and PORESET (see VIH row of Table 5)
Table 5: Changed IOL for 60x signals to 6.0 mA
Table 5: Moved QREQ to VOL: IOL= 3.2 mA
Table 5: Addition of critical interrupt (CINT) to IRQ5 for VOL (IOL = 6.0mA)
Table 10: Addition of
ΨJT and note 4
Sections 4.1–4.5: New
Table 12: Modified power values (+ 150mW to each)
Table 14: Addition of note 2. Changed PCI impedance to 27
Ω.
Table 9: Changes to sp36b, SP38a, sp38b, sp37a, sp39a, sp40 and sp41
Table 20: Changes to sp16a, sp18a, sp20 and sp21
Section 6.2: Addition of Note: CLKIN Jitter and Duty Cycle
Table 11: Changes to sp13 @ 66 and 83 MHz, sp14 @ 83 MHz
Table 12: Change to sp30 (data bus signals). Changes to sp33b. Removal of note 2.
Table 18 through Table 37: Modification of note 1 regarding CPU and CPM Fmin. Modification
to corresponding values in tables.
Table 23: Addition of note 1 to TRST (AH3) and PORESET (AG6)
Table 23: Addition of RXD3 to CPM port pin PB14. Previously omitted.
Table 23: Addition of critical interrupt (CINT) to B21 and U4. Previously omitted.
Table 23: Addition of note 5 to ‘No connect’ (AA1, AG4)
Table 25: Addition of note 1 to TRST (F22) and PORESET (B25)
Table 25: Addition of previously omitted signals that are multiplexed with CPM port pins:
PA6—FCC2_UT_RXADDR3
PA7—FCC2_UT_TXADDR3
PA8—FCC2_UT_TXADDR4
PB14—RXD3
PC19—SPICLK
PC22—FCC1_UT_TXPRTY
PC28—FCC2_UT_RXADDR4
Table 25: Removal of serial interface 1 (SI1) signals from port pins (see note 2 in Figure 1):
PA[6–9], PB[8–17, 20–25], PC[6–7, 10–13], PD[4, 10–13, 16, 23–28]
Table 25: Addition of critical interrupt (CINT) to AC1 and B14. Previously omitted.
Table 25: Addition of note 5 to ‘No connect’ (E17, C23)
Table 27. Document Revision History (continued)
Revision
Date
Substantive Changes
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