參數(shù)資料
型號(hào)： MPC8275CZQMIBA
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 19/83頁(yè)
文件大?。?/td> 0K
描述： IC MPU POWERQUICC II 516-PBGA
標(biāo)準(zhǔn)包裝： 40
系列： MPC82xx
處理器類(lèi)型： 32-位 MPC82xx PowerQUICC II
速度： 266MHz
電壓： 1.5V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 516-BBGA
供應(yīng)商設(shè)備封裝： 516-FPBGA（27x27）
包裝： 托盤(pán)
MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2
26
Freescale Semiconductor
Clock Configuration Modes
7
Clock Configuration Modes
This SoC includes the following clocking modes:
Local
PCI host
PCI agent
The clocking mode is set according to the following input pins as shown in the following table:
PCI_MODE
PCI_CFG[0]
PCI_MODCK
Input hold times
Boundary-scan data
TMS, TDI
tJTDXKH
tJTIXKH
10
—
ns
4, 7
Output valid times
Boundary-scan data
TDO
tJTKLDV
tJTKLOV
—
10
ns
5, 7
5. 7
Output hold times
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
1
—
ns
5, 7
JTAG external clock to output high impedance
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
1
10
ns
5, 6
1 All outputs are measured from the midpoint voltage of the falling/rising edge of t
TCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-
Ω load. Time-of-flight delays
must be added for trace lengths, vias, and connectors in the system.
2 The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t((first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference
(K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input
signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3 TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4 Non-JTAG signal input timing with respect to t
TCLK.
5 Non-JTAG signal output timing with respect to t
TCLK.
6 Guaranteed by design.
7 Guaranteed by design and device characterization.
Table 16. JTAG Timings1 (continued)
Parameter
Symbol2
Min
Max
Unit
Notes
相關(guān)PDF資料
PDF描述
AMC65DRES-S13 CONN EDGECARD 130POS .100 EXTEND
XF2M-3315-1A CONN FPC 33POS 0.5MM PITCH SMD
AMC50DRYN-S93 CONN EDGECARD 100PS DIP .100 SLD
IDT71T75902S85BG8 IC SRAM 18MBIT 85NS 119BGA
AMC49DRYI-S93 CONN EDGECARD 98POS DIP .100 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC8275CZQP 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications
MPC8275CZQT 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications
MPC8275CZUB 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications
MPC8275CZUE 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications
MPC8275CZUI 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*