
MOTOROLA
MPC8272 PowerQUICC II Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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3
Overview
Figure 1. Block Diagram
1.1
Features
The major features of the MPC8272 are as follows:
Dual-issue integer (G2_LE) core
— A core version of the MPC603e microprocessor
— System core microprocessor supporting frequencies of 266-400 MHz
— Separate 16-Kbyte data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
— PowerPC architecture-compliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
— Supports bus snooping for cache coherency
— Floating-point unit (FPU) supports floating-point arithmetic
— Support for cache locking
Low-power consumption
Separate power supply for internal logic (1.5 V) and for I/O (3.3 V)
16 Kbytes
I-Cache
G2_LE Core
I-MMU
16 Kbytes
D-Cache
D-MMU
Communication Processor Module (CPM)
Timers
Parallel I/O
Baud Rate
Generators
32-bit RISC Microcontroller
and Program ROM
Serial
DMA
60x-to-PCI
Bridge
Memory Controller
Clock Counter
System Functions
System Interface Unit
(SIU)
PCI Bus
32 bits, up to 66 MHz
FCC1
FCC2
SCC1
SCC3
SCC4
SMC1
SMC2
SPI
I
2
C
2 MII/RMII
Ports
Port
60x Bus
Interrupt
Controller
Time Slot Assigner
2 TDM Ports
Non-Multiplexed
I/O
Bus Interface Unit
Virtual
IDMAs
16 KB
Data
RAM
Security (SEC)
1
2
1 8-bit Utopia
Serial interfSerial Interface
4 KB
Instruction
RAM
Note
1
MPC8272/8248 only
2
MPC8272/8271 only
USB 2.0
F
Freescale Semiconductor, Inc.
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