參數(shù)資料
型號(hào): MPC8270CVVQLDA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 333 MHz, RISC PROCESSOR, PBGA480
封裝: 37.50 X 37.50 MM, 1.55 MM HEIGHT, 1.27 MM PITCH, ROHS COMPLIANT, FTBGA-480
文件頁數(shù): 74/83頁
文件大?。?/td> 1689K
代理商: MPC8270CVVQLDA
MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 1.6
76
Freescale Semiconductor
Ordering Information
10 Ordering Information
Figure 19 provides an example of the Freescale part numbering nomenclature for the MPC8280. In addition to the
processor frequency, the part numbering scheme also consists of a part modifier that indicates any enhancement(s)
in the part from the original production design. Each part number also contains a revision code that refers to the die
mask revision number and is specified in the part numbering scheme for identification purposes only. For more
information, contact your local Freescale sales office.
Figure 19. Freescale Part Number Key
11 Document Revision History
Table 25. Document Revision History
Revision
Date
Substantive Changes
0.1
Initial public release
0.2
11/2002 Table 23, “VR Pinout”: Addition of C18 to the Ground (GND) pin list (page 63)
0.3
6/2003
Removal of notes stating “no local bus” on VR-package devices. The MPC8270VR and the
MPC8275VR have local bus support.
References to “G2 core” changed to “G2_LE core.” Refer to the G2 Core Reference Manual
(G2CORERM/D).
Addition of VCCSYN to “Note” below Table 4, and to note 3 of Table 5
Table 5: Addition of note 1
Table 6: Addition of
θ
JB and θJC. Modifications to ZU package values.
Table 7: Addition of various configurations, Modification of values. Addition of note 3.
Table 9: Addition of 66 MHZ and 100 MHz values. Addition of sp42a/sp43a.
Table 10: Addition of 66 MHZ and 100 MHz values
Table 12: sp30 values. sp33b @100 MHz value. Removal of previous note 2. Modification of
current note 2.
Section 6.2: Addition of note on PCI timing
Table 16, Table 17, Table 18, Table 19, Table 20: Addition of note 1 concerning minimum
operating frequencies
Addition of statement before clock tables about selection of clock configuration and input
frequency
Table 21 and Table 23: Addition of note 1 to CPM pins
Product Code
Device Number
Package
Processor Frequency
Die Revision Level
MPC 82XX C ZU XXX
(CPU/CPM/Bus)
X
Temperature Range
Blank = 0T
A
to 105Tj
C = (-40)T
A
– 105Tj
ZU = 480 TBGA Lead spheres
VR = 516 PBGA Lead-free spheres
ZQ = 516 PBGA Lead spheres
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