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參數(shù)資料
| 型號： | MPC8266ACZU |
| 廠商： | Motorola, Inc. |
| 英文描述： | MPC826xA (HiP4) Family Hardware Specifications |
| 中文描述： | MPC826xA（HiP4）家庭硬件規(guī)格 |
| 文件頁數(shù)： | 20/48頁 |
| 文件大?。?/td> | 315K |
| 代理商： | MPC8266ACZU |
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20
MPC826xA (HiP4) Family Hardware Specifications
MOTOROLA
Clock Configuration Modes
NOTE
The UPM machine outputs change on the internal tick determined by the
memory controller programming; the AC specifications are relative to the
internal tick. Note that SDRAM and GPCM machine outputs change on
CLKin’s rising edge.
1.3
Clock Configuration Modes
To configure the main PLL multiplication factor and the core, CPM, and 60x bus frequencies, the
MODCK[1–3] pins are sampled while HRESET is asserted. Table 12 lists the eight basic configuration
modes. Table 13 lists the other modes that are available by using the configuration pin (RSTCONF) and
driving four bits from hardware configuration word on the data bus.
Note that the MPC8265 and the MPC8266 have two additional clocking modes—PCI agent and PCI host.
Refer to Section 1.3.2, “PCI Mode” on page 23 for information.
NOTE
Clock configurations change only after POR is asserted.
1.3.1
Local Bus Mode
Table 12 describes default clock modes for the MPC826xA.
Table 13 describes all possible clock configurations when using the hard reset configuration sequence.
Note that basic modes are shown in boldface type. The frequencies listed are for the purpose of illustration
only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed
the frequency rating of the user’s device.
Table 12. Clock Default Modes
MODCK[1–3]
Input Clock
Frequency
CPM Multiplication
Factor
CPM
Frequency
Core Multiplication
Factor
Core
Frequency
000
33 MHz
3
100 MHz
4
133 MHz
001
33 MHz
3
100 MHz
5
166 MHz
010
33 MHz
4
133 MHz
4
133 MHz
011
33 MHz
4
133 MHz
5
166 MHz
100
66 MHz
2
133 MHz
2.5
166 MHz
101
66 MHz
2
133 MHz
3
200 MHz
110
66 MHz
2.5
166 MHz
2.5
166 MHz
111
66 MHz
2.5
166 MHz
3
200 MHz
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