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| 型號： | MPC8265AZUPJDC |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 12/50頁 |
| 文件大小： | 0K |
| 描述： | IC MPU POWERQUICC II 480-TBGA |
| 標準包裝： | 21 |
| 系列： | MPC82xx |
| 處理器類型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 300MHz |
| 電壓： | 2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 480-LBGA |
| 供應(yīng)商設(shè)備封裝： | 408-TBGA（37.5x37.5） |
| 包裝： | 托盤 |
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MPC8260A PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2.0
2
Freescale Semiconductor
Features
Figure 1 shows the block diagram for the MPC8266, the HiP4 superset device. Shaded portions indicate
functionality that is not available on all devices; refer to the notes.
Figure 1. MPC8266 Block Diagram
1
Features
The major features of the MPC826xA family are as follows:
Dual-issue integer core
— A core version of the EC603e microprocessor
— System core microprocessor supporting frequencies of 150–300 MHz
— Separate 16-Kbyte data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
16 Kbytes
G2 Core
I-Cache
I-MMU
16 Kbytes
D-Cache
D-MMU
Communication Processor Module (CPM)
Timers
Parallel I/O
Baud Rate
Generators
32 Kbytes
32-bit RISC Microcontroller
and Program ROM
Serial
DMAs
4 Virtual
IDMAs
60x-to-PCI
Bridge2,3
Bridge
Memory Controller
Clock Counter
System Functions
System Interface Unit
(SIU)
Local Bus
32 bits, up to 83 MHz
PCI Bus2,3
32 bits, up to 66 MHz
or
MCC1
4
MCC2
FCC1
FCC2
FCC3
4
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
SPI
I2C
Serial Interface
3 MII
2 UTOPIA
Ports
Ports6
60x Bus
Microcode
IMA1,3
Dual-Port RAM
Interrupt
Controller
Time Slot Assigner
TC Layer Hardware1,3
8 TDM Ports5
Non-Multiplexed
I/O
60x-to-Local
Bus Interface Unit
Notes:
1 MPC8264
2 MPC8265
3 MPC8266
4 Not on MPC8255
5 4 TDM ports on the MPC8255
6 2 MII ports on the MPC8255
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