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參數(shù)資料
| 型號： | MPC8260ZUIFBXXX |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA480 |
| 封裝： | 37.50 X 37.50 MM, 1.27 MM PITCH, TBGA-480 |
| 文件頁數(shù)： | 8/40頁 |
| 文件大?。?/td> | 1069K |
| 代理商： | MPC8260ZUIFBXXX |
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MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 1.3
16
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 10 lists SIU output characteristics.
Activating data pipelining (setting BRx[DR] in the memory controller)
improves the AC timing. When data pipelining is activated, sp12 can be
used for data bus setup even when ECC or PARITY are used. Also, sp33a
can be used as the AC specification for DP signals.
Figure 8 shows TDM input and output signals.
Figure 8. TDM Signal Diagram
Table 10. AC Characteristics for SIU Outputs 1
1
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
Timings are measured at the pin.
NOTE
Spec Number
Characteristic
Max Delay (ns) Min Delay (ns)
Max
Min
66 MHz
sp31
sp30
PSDVAL/TEA/TA
10
0.5
sp32
sp30
ADD/ADD_atr./BADDR/CI/GBL/WT
8
0.5
sp33a
sp30
Data bus
8
0.5
sp33b
sp30
DP
12
0.5
sp34
sp30
memc signals/ALE
6
0.5
sp35
sp30
all other signals
7.5
0.5
Serial CLKin
TDM input signals
TDM output signals
sp20
sp21
sp40/sp41
Note: There are four possible TDM timing conditions:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
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