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參數(shù)資料
| 型號： | MPC8260CZU |
| 廠商： | Motorola, Inc. |
| 英文描述： | MPC826xA (HiP4) Family Hardware Specifications |
| 中文描述： | MPC826xA（HiP4）家庭硬件規(guī)格 |
| 文件頁數(shù)： | 17/48頁 |
| 文件大?。?/td> | 315K |
| 代理商： | MPC8260CZU |
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MOTOROLA
MPC826xA (HiP4) Family Hardware Specifications
17
Electrical and Thermal Characteristics
Table 10 lists SIU input characteristics.
Table 10 lists SIU output characteristics.
NOTE
Activating data pipelining (setting BR
x
[DR] in the memory controller)
improves the AC timing. When data pipelining is activated, sp12 can be
used for data bus setup even when ECC or PARITY are used. Also, sp33a
can be used as the AC specification for DP signals.
Figure 9 shows the interaction of several bus signals.
Table 9. AC Characteristics for SIU Inputs
1
1
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.
Timings are measured at the pin.
Spec Number
Characteristic
Setup (ns)
Hold (ns)
Max
Min
66 MHz 83 MHz 66 MHz 83 MHz
sp11
sp10
AACK/ARTRY/TA/TS/TEA/DBG/BG/BR
6
5
0.5
0.5
sp12
sp10
Data bus in normal mode
5
4
0.5
0.5
sp13
sp10
Data bus in ECC and PARITY modes
8
6
0.5
0.5
sp14
sp10
DP pins
7
6
0.5
0.5
sp15
sp10
All other pins
5
4
0.5
0.5
Table 10. AC Characteristics for SIU Outputs
1
1
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the
signal. Timings are measured at the pin.
Spec Number
Characteristic
Max Delay (ns)
Min Delay (ns)
Max
Min
66 MHz 83 MHz 66 MHz 83 MHz
sp31
sp30
PSDVAL/TEA/TA
7
6
0.5
0.5
sp32
sp30
ADD/ADD_atr./BADDR/CI/GBL/WT
8
6.5
0.5
0.5
sp33a
sp30
Data bus
6.5
6.5
0.5
0.5
sp33b
sp30
DP
8
7
0.5
0.5
sp34
sp30
Memory controller signals/ALE
6
5
0.5
0.5
sp35
sp30
All other signals
6
5.5
0.5
0.5
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