參數(shù)資料
型號(hào)： MPC8260AZUPJDB
廠商： Freescale Semiconductor
文件頁數(shù)： 14/50頁
文件大小： 0K
描述： IC MPU POWERQUICC II 480-TBGA
標(biāo)準(zhǔn)包裝： 21
系列： MPC82xx
處理器類型： 32-位 MPC82xx PowerQUICC II
速度： 300MHz
電壓： 2V
安裝類型： 表面貼裝
封裝/外殼： 480-LBGA
供應(yīng)商設(shè)備封裝： 408-TBGA（37.5x37.5）
包裝： 托盤
配用： MPC8260ADS-TCOM-ND - BOARD DEV ADS POWERQUICC II
MPC8260A PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2.0
Freescale Semiconductor
21
Electrical and Thermal Characteristics
Figure 11 shows signal behavior in MEMC mode.
Figure 11. MEMC Mode Diagram
NOTE
Generally, all MPC826xA bus and system output signals are driven from the
rising edge of the input clock (CLKin). Memory controller signals,
however, trigger on four points within a CLKin cycle. Each cycle is divided
by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising
edge, and T3 at the falling edge, of CLKin. However, the spacing of T2 and
T4 depends on the PLL clock ratio selected, as shown in Table 11.
Figure 12 is a graphical representation of Table 11.
Figure 12. Internal Tick Spacing for Memory Controller Signals
Table 11. Tick Spacing for Memory Controller Signals
PLL Clock Ratio
Tick Spacing (T1 Occurs at the Rising Edge of CLKin)
T2
T3
T4
1:2, 1:3, 1:4, 1:5, 1:6
1/4 CLKin
1/2 CLKin
3/4 CLKin
1:2.5
3/10 CLKin
1/2 CLKin
8/10 CLKin
1:3.5
4/14 CLKin
1/2 CLKin
11/14 CLKin
CLKin
V_CLK
Memory controller signals
sp34/sp30
CLKin
T1
T2
T3
T4
CLKin
T1
T2
T3
T4
for 1:2.5
for 1:3.5
CLKin
T1
T2
T3
T4
for 1:2, 1:3, 1:4, 1:5, 1:6
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