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    參數(shù)資料
    型號(hào): MPC8260AVRIFBX
    廠商: FREESCALE SEMICONDUCTOR INC
    元件分類: 微控制器/微處理器
    英文描述: 32-BIT, 200 MHz, RISC PROCESSOR, PBGA516
    封裝: PLASTIC, BGA-516
    文件頁數(shù): 45/52頁
    文件大?。?/td> 884K
    代理商: MPC8260AVRIFBX
    MPC8260A PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 1.1
    Freescale Semiconductor
    5
    Features
    – Transparent
    – UART (low-speed operation)
    — One serial peripheral interface identical to the MPC860 SPI
    — One inter-integrated circuit (I2C) controller (identical to the MPC860 I2C controller)
    – Microwire compatible
    – Multiple-master, single-master, and slave modes
    — Up to eight TDM interfaces (four on the MPC8255)
    – Supports two groups of four TDM channels for a total of eight TDMs
    – 2,048 bytes of SI RAM
    – Bit or byte resolution
    – Independent transmit and receive routing, frame synchronization
    – Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN
    primary rate, Freescale interchip digital link (IDL), general circuit interface (GCI), and
    user-defined TDM serial interfaces
    — Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs,
    SCCs, SMCs, and serial channels
    — Four independent 16-bit timers that can be interconnected as two 32-bit timers
    Additional features of the MPC826xA family are as follows:
    CPM
    — 32-Kbyte dual-port RAM
    — Additional MCC host commands
    — Eight transfer transmission convergence (TC) layers between the TDMs and FCC2 to support
    inverse multiplexing for ATM capabilities (IMA) (MPC8264 and MPC8266 only)
    CPM multiplexing
    — FCC2 can also be connected to the TC layer.
    TC layer (MPC8264 and MPC8266 only)
    — Each of the 8 TDM channels is routed in hardware to a TC layer block
    – Protocol-specific overhead bits may be discarded or routed to other controllers by the SI
    – Performing ATM TC layer functions (according to ITU-T I.432)
    – Transmit (Tx) updates
    - Cell HEC generation
    - Payload scrambling using self synchronizing scrambler (programmable by the user)
    - Coset generation (programmable by the user)
    - Cell rate by inserting idle/unassigned cells
    – Receive (Rx) updates
    - Cell delineation using bit by bit HEC checking and programmable ALPHA and DELTA
    parameters for the delineation state machine
    - Payload descrambling using self synchronizing scrambler (programmable by the user)
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