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參數(shù)資料
| 型號： | MPC8255AZUIHBX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA480 |
| 封裝： | 37.50 X 37.50 MM, 1.55 MM HEIGHT, 1.27 MM PITCH, TBGA-480 |
| 文件頁數(shù)： | 11/36頁 |
| 文件大小： | 683K |
| 代理商： | MPC8255AZUIHBX |
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MOTOROLA
MPC8255 Hardware Specifications
19
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Clock Configuration Modes
0110_111
66 MHz
2.5
166 MHz
4
266 MHz
0111_000
66 MHz
2.5
166 MHz
4.5
300 MHz
0111_001
66 MHz
3
200 MHz
2
133 MHz
0111_010
66 MHz
3
200 MHz
2.5
166 MHz
0111_011
66 MHz
3
200 MHz
3
200 MHz
0111_100
66 MHz
3
200 MHz
3.5
233 MHz
0111_101
66 MHz
3
200 MHz
4
266 MHz
0111_110
66 MHz
3
200 MHz
4.5
300 MHz
0111_111
66 MHz
3.5
233 MHz
2
133 MHz
1000_000
66 MHz
3.5
233 MHz
2.5
166 MHz
1000_001
66 MHz
3.5
233 MHz
3
200 MHz
1000_010
66 MHz
3.5
233 MHz
3.5
233 MHz
1000_011
66 MHz
3.5
233 MHz
4
266 MHz
1000_100
66 MHz
3.5
233 MHz
4.5
300 MHz
1100_0004
66 MHz
2
133 MHz
Bypass
66 MHz
1100_0014
66 MHz
2.5
166 MHz
Bypass
66 MHz
1100_0104
66 MHz
3
200 MHz
Bypass
66 MHz
1 Because of speed dependencies, not all of the possible configurations in Table 13 are applicable.
2 The user should choose the input clock frequency and the multiplication factors such that the frequency of the
CPU is equal to or greater than 133 MHz (150 MHz for extended temperature parts) and the CPM ranges
between 66–233 MHz.
3 Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so that
the resulting configuration does not exceed the frequency rating of the user’s part.
Example. If a part is rated at 266 MHz CPU, 200 MHz CPM, and 66 MHz bus, any of the following are possible
(note that the three input clock frequencies are only three of many possible input clock frequencies):
1. 66 MHz input clock and MODCK_H–MODCK_L[0111–101] (with a core multiplication factor of 4 and a CPM
multiplication factor of 3). The resulting configuration equals the part’s maximum possible frequencies of
266 MHz CPU, 200 MHz CPM, and 66 MHz bus.
2. 50 MHz input clock and MODCK_H–MODCK_L[0111–101] to achieve a configuration of 200 MHz CPU,
150 MHz CPM, and 50 MHz bus.
3. 40 MHz input clock and MODCK_H–MODCK_L[0010–011] to achieve a configuration of 200 MHz CPU,
160 MHz CPM, and 40 MHz bus.
Note that with each example, any one of several values for MODCK_H–MODCK_L could possibly be used as
long as the resulting configuration does not exceed the part’s rating.
4 At this mode the CPU PLL is bypassed (the CPU frequency equals the bus frequency).
Table 13. Clock Configuration Modes1 (Continued)
MODCK_H–MODCK[1–3]
Input Clock
Frequency2,3
CPM Multiplication
Factor2
CPM
Frequency2
Core Multiplication
Factor2
Core
Frequency2
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