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  • 參數(shù)資料
    型號: MPC8248ZQE
    廠商: Motorola, Inc.
    英文描述: MPC8272 PowerQUICC II Family Hardware Specifications
    中文描述: MPC8272的PowerQUICC II系列硬件規(guī)格
    文件頁數(shù): 19/56頁
    文件大小: 539K
    代理商: MPC8248ZQE
    19
    MPC8272 PowerQUICC II Family Hardware Specifications
    PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
    For More Information On This Product,
    Go to: www.freescale.com
    MOTOROLA
    AC Electrical Characteristics
    6.2
    SIU AC Characteristics
    Table 11 lists SIU input characteristics.
    NOTE: PCI AC Timing
    The MPC8272 meets the timing requirements of
    PCI Specification
    Revision 2.2
    . Refer to Section 7, “Clock Configuration Modes” and “Note:
    Tval (Output Hold)” to determine if a specific clock configuration is
    compliant.
    Table 12 lists SIU output characteristics.
    NOTE
    Activating data pipelining (setting BR
    x
    [DR] in the memory controller)
    improves the AC timing.
    Figure 9 shows the interaction of several bus signals.
    Table 11. AC Characteristics for SIU Inputs
    1
    1
    Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings
    are measured at the pin.
    Spec Number
    Characteristic
    Value (ns)
    Setup
    Hold
    Setup
    Hold
    66
    MHz
    83
    MHz
    100
    MHz
    66
    MHz
    83
    MHz
    100
    MHz
    sp11
    sp10
    AACK/TA/TS/DBG/BG/BR
    6
    5
    3.5
    0.5
    0.5
    0.5
    sp11a
    sp10
    ARTRY/ TEA
    6
    5
    4
    0.5
    0.5
    0.5
    sp12
    sp10
    Data bus in normal mode
    5
    4
    3.5
    0.5
    0.5
    0.5
    sp13
    sp10
    Data bus in pipeline mode
    5
    4
    2.5
    0.5
    0.5
    0.5
    sp15
    sp10
    All other pins
    5
    4
    3.5
    0.5
    0.5
    0.5
    Table 12. AC Characteristics for SIU Outputs
    1
    1
    Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
    Timings are measured at the pin.
    2
    To achieve 1 ns of hold time at 66.67/83.33/100 MHZ, a minimum loading of 20 pF is required.
    Spec Number
    Characteristic
    Value (ns)
    Max
    Min
    Maximum Delay
    Minimum Delay
    66
    MHz
    83
    MHz
    100
    MHz
    66
    MHz
    83
    MHz
    100
    MHz
    sp31
    sp30 PSDVAL/TEA/TA
    7
    6
    5.5
    1
    1
    1
    sp32
    sp30
    ADD/ADD_atr./BADDR/CI/GBL/WT
    8
    6.5
    5.5
    1
    1
    1
    sp33
    sp30 Data bus
    2
    6.5
    6.5
    5.5
    0.5
    0.5
    0.5
    sp34
    sp30
    Memory controller signals/ALE
    6
    5.5
    5.5
    1
    1
    1
    sp35
    sp30
    All other signals
    6
    5.5
    5.5
    1
    1
    1
    F
    Freescale Semiconductor, Inc.
    n
    .
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