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    參數(shù)資料
    型號: MPC8248VRM
    廠商: Motorola, Inc.
    英文描述: MPC8272 PowerQUICC II Family Hardware Specifications
    中文描述: MPC8272的PowerQUICC II系列硬件規(guī)格
    文件頁數(shù): 22/56頁
    文件大?。?/td> 539K
    代理商: MPC8248VRM
    22
    MPC8272 PowerQUICC II Family Hardware Specifications
    PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
    For More Information On This Product,
    Go to: www.freescale.com
    MOTOROLA
    Clock Configuration Modes
    7
    As shown in Table 14, the clocking mode is set according to two sources:
    Clock Configuration Modes
    PCI_CFG[0]— An input signal. Also defined as “PCI_HOST_EN.” Refer to the Chapter 6,
    “External Signals,” and Chapter 9, “PCI Bridge,” in the
    MPC8272 PowerQUICC II Family
    Reference Manual
    .
    PCI_MODCK—Bit 27 in the Hard Reset Configuration Word. Refer to Chapter 5, “Reset,” in the
    MPC8272 PowerQUICC II Family Reference Manual
    .
    Within each mode, the configuration of bus, core, PCI, and CPM frequencies is determined by seven bits
    during the power-on reset—three hardware configuration pins (MODCK[1–3]) and four bits from hardware
    configuration word[28–31] (MODCK_H). Both the PLLs and the dividers are set according to the selected
    clock operation mode as described in the following sections.
    NOTE
    Clock configurations change only after PORESET is asserted.
    NOTE: Tval (Output Hold)
    The minimum Tval = 2 when PCI_MODCK = 1, and the minimum
    Tval = 1 when PCI_MODCK = 0. Therefore, designers should use clock
    configurations that fit this condition to achieve PCI-compliant AC timing.
    7.1
    PCI Host Mode
    Table 15 and Table 16 show configurations for PCI host mode. The frequency values listed are for the
    purpose of illustration only. Users must select a mode and input bus frequency so that the resulting
    configuration does not exceed the frequency rating of the user’s device. Note that in PCI host mode the input
    clock is the bus clock.
    Table 14. MPC8272 Clocking Modes
    Pins
    Clocking Mode
    PCI Clock Frequency
    Range (MHZ)
    Reference
    PCI_CFG[0]
    1
    1
    PCI_HOST_EN
    2
    Determines PCI clock frequency range.
    PCI_MODCK
    2
    0
    0
    PCI host
    50–66
    Table 15
    0
    1
    25–50
    Table 16
    1
    0
    PCI agent
    50–66
    Table 17
    1
    1
    25–50
    Table 18
    F
    Freescale Semiconductor, Inc.
    n
    .
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