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參數(shù)資料
| 型號： | MPC8248CZQPIEA |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 59/61頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU POWERQUICC II 516-PBGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | MPC82xx |
| 處理器類型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 300MHz |
| 電壓： | 1.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 516-BBGA |
| 供應(yīng)商設(shè)備封裝： | 516-FPBGA（27x27） |
| 包裝： | 托盤 |
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MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
7
Operating Conditions
PCI bridge
— PCI Specification revision 2.2-compliant and supports frequencies up to 66 MHz
— On-chip arbitration
— Support for PCI to 60x memory and 60x memory to PCI streaming
— PCI host bridge or peripheral capabilities
— Includes four DMA channels for the following transfers:
– PCI-to-60x to 60x-to-PCI
– 60x-to-PCI to PCI-to-60x
– PCI-to-60x to PCI-to-60x
– 60x-to-PCI to 60x-to-PCI
— Includes the configuration registers required by the PCI standard (which are automatically
loaded from the EPROM to configure the MPC8272) and message and doorbell registers
— Supports the I2O standard
— Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0
August 3, 1998)
— Support for 66 MHz, 3.3 V specification
— 60x-PCI bus core logic, which uses a buffer pool to allocate buffers for each port
2
Operating Conditions
This table shows the maximum electrical ratings.
Table 3. Absolute Maximum Ratings1
1 Absolute maximum ratings are stress ratings only; functional operation (see Table 4) at the maximums is not
guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage.
Rating
Symbol
Value
Unit
Core supply voltage2
2 Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V during normal operation. It is recommended that
VDD/VCCSYN should be raised before or simultaneous with VDDH during power-on reset. VDD/VCCSYN may
exceed VDDH by more than 0.4 V during power-on reset for no more than 100 ms.
VDD
–0.3 – 2.25
V
PLL supply voltage2
VCCSYN
–0.3 – 2.25
V
I/O supply voltage3
3 Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec. VDDH should
not exceed VDD/VCCSYN by more than 2.5 V during normal operation.
VDDH
–0.3 – 4.0
V
Input voltage4
4 Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.
VIN
GND(–0.3) – 3.6
V
Junction temperature
Tj
120
°C
Storage temperature range
TSTG
(–55) – (+150)
°C
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