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  • 參數(shù)資料
    型號: MPC8247ZQI
    廠商: Motorola, Inc.
    英文描述: MPC8272 PowerQUICC II Family Hardware Specifications
    中文描述: MPC8272的PowerQUICC II系列硬件規(guī)格
    文件頁數(shù): 21/56頁
    文件大?。?/td> 539K
    代理商: MPC8247ZQI
    21
    MPC8272 PowerQUICC II Family Hardware Specifications
    PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
    For More Information On This Product,
    Go to: www.freescale.com
    MOTOROLA
    AC Electrical Characteristics
    NOTE
    Generally, all MPC8272 bus and system output signals are driven from the
    rising edge of the input clock (CLKin). Memory controller signals,
    however, trigger on four points within a CLKin cycle. Each cycle is
    divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the
    rising edge, and T3 at the falling edge, of CLKin. However, the spacing of
    T2 and T4 depends on the PLL clock ratio selected, as shown in Table 13.
    Figure 11 is a representation of the information in Table 13.
    Figure 11. Internal Tick Spacing for Memory Controller Signals
    NOTE
    The UPM machine outputs change on the internal tick determined by the
    memory controller programming; the AC specifications are relative to the
    internal tick. Note that SDRAM and GPCM machine outputs change on
    CLKin’s rising edge.
    Table 13. Tick Spacing for Memory Controller Signals
    PLL Clock Ratio
    Tick Spacing (T1 Occurs at the Rising Edge of CLKin)
    T2
    T3
    T4
    1:2, 1:3, 1:4, 1:5, 1:6
    1/4 CLKin
    1/2 CLKin
    3/4 CLKin
    1:2.5
    3/10 CLKin
    1/2 CLKin
    8/10 CLKin
    1:3.5
    4/14 CLKin
    1/2 CLKin
    11/14 CLKin
    CLKin
    T1
    T2
    T3
    T4
    CLKin
    T1
    T2
    T3
    T4
    for 1:2.5
    for 1:3.5
    CLKin
    T1
    T2
    T3
    T4
    for 1:2, 1:3, 1:4, 1:5, 1:6
    F
    Freescale Semiconductor, Inc.
    n
    .
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