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參數(shù)資料
| 型號： | MPC8247 |
| 廠商： | Motorola, Inc. |
| 英文描述： | MPC8272 PowerQUICC II Family Hardware Specifications |
| 中文描述： | MPC8272的PowerQUICC II系列硬件規(guī)格 |
| 文件頁數(shù)： | 38/56頁 |
| 文件大?。?/td> | 1090K |
| 代理商： | MPC8247 |
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38
MPC8272 PowerQUICC II Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Clock Configuration Modes
1100_000
Reserved
1100_001
Reserved
1100_010
Reserved
1
The “l(fā)ow” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency
guarantees the required minimum CPU operating frequency. Minimum CPU frequency is determined by the clock
mode. For modes with a CPU multiplication factor
≤
3, the minimum CPU frequency is 125 MHz or 150 MHz, as
shown in the table. For modes with a CPU multiplication factor
≥
3.5, the minimum CPU frequency is 250 MHz.
The “high” values are for the purpose of illustration only. Users must select a mode and input bus frequency so
that the resulting configuration does not exceed the frequency rating of the user’s device.
2
PCI_MODCK determines the PCI clock frequency range. Refer to Table 17 for higher range configurations.
3
MODCK_H = hard reset configuration word [28–31] (refer to Section 5.4 in the
MPC8260 User’s Manual
).
MODCK[1-3] = three hardware configuration pins.
4
CPM multiplication factor = CPM clock/bus clock
5
CPU multiplication factor = Core PLL multiplication factor
Table 18. Clock Configurations for PCI Agent Mode (PCI_MODCK=1)
1, 2
(continued)
Mode
3
PCI Clock
(MHz)
CPM
Multiplication
Factor
4
CPM Clock
(MHz)
CPU
Multiplication
Factor
5
CPU Clock
(MHz)
Bus
Division
Factor
Bus Clock
(MHz)
MODCK_H-
MODCK[1-3]
Low
High
Low
High
Low
High
Low
High
F
Freescale Semiconductor, Inc.
n
.
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