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參數(shù)資料
| 型號(hào)： | MPC8245LZU300D |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 39/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 300MHZ 352-TBGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | MPC82xx |
| 處理器類型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 300MHz |
| 電壓： | 1.8V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 352-LBGA |
| 供應(yīng)商設(shè)備封裝： | 352-TBGA（35x35） |
| 包裝： | 托盤 |
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MPC8245 Integrated Processor Hardware Specifications, Rev. 10
44
Freescale Semiconductor
System Design
7
System Design
This section provides electrical and thermal design recommendations for successful application of the
MPC8245.
7.1
PLL Power Supply Filtering
The AV
DD and AVDD2 power signals on the MPC8245 provide power to the peripheral logic/memory bus
PLL and the MPC603e processor PLL. To ensure stability of the internal clocks, the power supplied to the
AVDD and AVDD2 input signals should be filtered of any noise in the 500-kHz to 10-MHz resonant
frequency range of the PLLs. Two separate circuits similar to the one shown in Figure 25 using surface
mount capacitors with minimum effective series inductance (ESL) is recommended for AVDD and AVDD2
power signal pins. Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital
Design: A Handbook of Black Magic (Prentice Hall, 1993), using multiple small capacitors of equal value
is recommended over using multiple values.
Place the circuits as closely as possible to the respective input signal pins to minimize noise coupled from
nearby circuits. Routing from the capacitors to the input signal pins should be as direct as possible with
minimal inductance of vias.
Figure 25. PLL Power Supply Filter Circuit
7.2
Decoupling Recommendations
Due to its dynamic power management feature, large address and data buses, and high operating
frequencies, the MPC8245 can generate transient power surges and high frequency noise in its power
supply, especially while driving large capacitive loads. This noise must be prevented from reaching other
components in the MPC8245 system, and the MPC8245 itself requires a clean, tightly regulated source of
power. Therefore, place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pin.
These decoupling capacitors should receive their power from dedicated power planes in the PCB, with
short traces to minimize inductance. These capacitors should have a value of 0.1 F. Only ceramic SMT
(surface mount technology) capacitors should be used to minimize lead inductance, preferably 0508 or
0603, oriented such that connections are made along the length of the part.
In addition, several bulk storage capacitors should be distributed around the PCB, feeding the VDD, OVDD,
GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors
should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary.
They should also be connected to the power and ground planes through two vias to minimize inductance.
Suggested bulk capacitors: 100–330 F (AVX TPS tantalum or Sanyo OSCON).
VDD
AVDD or AVDD2
2.2 F
GND
Low ESL Surface Mount Capacitors
10
Ω
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