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參數(shù)資料
| 型號： | MPC8245ARZU466D |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT00; Number of Contacts:19; Connector Shell Size:14; Connecting Termination:Solder; Circular Shell Style:Wall Mount Receptacle |
| 中文描述： | 型號規(guī)格為MPC8245ARZUnnnX系列 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 183K |
| 代理商： | MPC8245ARZU466D |
MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series, Rev. 2
4
Freescale Semiconductor
General Parameters
4.1.5
Power Characteristics
The AC electrical characteristics and AC timing for the parts described in this document are unaffected, and comply
with the
MPC8245 Integrated Processor Hardware Specifications
.
Table 5
provides the power consumption for the
MPC8245 part numbers described herein.
Table 5. Power Consumption
Mode
PCI Bus Clock/Memory Bus Clock
CPU Clock Frequency (MHz)
Unit
Notes
66/133/399
66/133/466
Typical
2.8
3.2
W
1, 5
Max—CFP
3.3
3.6
W
1, 2
Max—INT
2.8
3.1
W
1, 3
Doze
1.9
2.1
W
1, 4, 6
Nap
0.7
0.8
W
1, 4, 6
Sleep
0.4
0.4
W
1, 4, 6
I/O Power Supplies
10
Mode
Range
Range
Unit
Notes
Typ—OV
DD
140–360
140–360
mW
7, 8
Typ—GV
DD
340–920
340–930
mW
7, 9
Notes:
1.
2.
The values include V
DD
, AV
DD
, and AV
DD
2, but do not include I/O supply power.
Maximum—FP power is measured at V
DD
= 2.1 V with dynamic power management enabled while running an entirely
cache-resident, looping, floating point multiplication instruction.
Maximum—INT power is measured at V
DD
= 2.1 V with dynamic power management enabled while running entirely
cache-resident, looping, integer instructions.
Power saving mode maximums are measured at V
DD
= 2.1 V while the device is in doze, nap, or sleep mode.
Typical power is measured at V
DD
= AV
DD
= 2.1 V, OV
DD
= 3.3 V where a nominal FP value, a nominal INT value, and a
value where there is a continuous flush of cache lines with alternating ones and zeros on 64-bit boundaries to local memory
are averaged.
Power saving mode data measured with only two PCI_CLKs and two SDRAM_CLKs enabled.
The typical minimum I/O power values was the result of the MPC8245 performing cache resident integer operations at the
slowest frequency combination of 33:66:200 (PCI:Mem:CPU) MHz.
The typical maximum OV
DD
value resulted from the MPC8245 operating at the fastest frequency combination of
66:133:399 (PCI:Mem:CPU) MHz for the 400-MHz part, 66:133:466 (PCI:Mem:CPU) MHz for the 466-MHz part, and
performing continuous flushes of cache lines with alternating ones and zeros to PCI memory.
The typical maximum GV
DD
value resulted from the MPC8245 operating at the fastest frequency combination of
66:133:399 (PCI:Mem:CPU) MHz for the 400-MHz part, 66:133:466 (PCI:Mem:CPU) MHz for the 466-MHz part, and
performing continuous flushes of cache lines with alternating ones and zeros on 64-bit boundaries to local memory.
10. Power consumption of PLL supply pins (AV
DD
and AV
DD
2) < 15 mW that the design guarantees but were not tested.
3.
4.
5.
6.
7.
8.
9.
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