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參數(shù)資料
| 型號(hào)： | MPC8241LVR200X |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA357 |
| 封裝： | 25 X 25 MM, 1.27 MM PITCH, PLASTIC, BGA-357 |
| 文件頁數(shù)： | 38/60頁 |
| 文件大?。?/td> | 752K |
| 代理商： | MPC8241LVR200X |
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43
MPC8241 Integrated Processor Hardware Specifications
MOTOROLA
PLL Configuration
1F
111118
Not usable
Off
Notes:
1.
Limited by maximum PCI input frequency (66 MHz).
2.
Note the impact of the relevant revisions for modes 7 and 1E.
3.
Limited by minimum memory VCO frequency (132 MHz).
4.
Limited due to maximum memory VCO frequency (352 MHz).
5.
Limited by maximum CPU operating frequency.
6.
Limited by minimum CPU VCO frequency (300 MHz).
7.
Limited by maximum CPU VCO frequency (704 MHz).
8.
In clock off mode, no clocking occurs inside the MPC8241 regardless of the PCI_SYNC_IN input.
9.
Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for
clarity.
10. PLL_CFG[0:4] settings not listed are reserved.
11. Multiplier ratios for this PLL_CFG[0:4] setting are different from the MPC8240 and are not backwards-compatible.
12. PCI_SYNC_IN range for this PLL_CFG[0:4] setting is different from the MPC8240 and may not be fully
backwards-compatible.
13. Bits 7–4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value.
14. In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic
PLL is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for hardware
modeling support. The AC timing specifications given in this document do not apply in PLL bypass mode.
15. In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the
peripheral logic PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In this
mode, the OSC_IN input signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode operation, and
the processor PLL is disabled. The PCI_SYNC_IN and OSC_IN input clocks must be externally synchronized.
This mode is intended for hardware modeling support. The AC timing specifications given in this document do not
apply in dual PLL bypass mode.
16. Limited by maximum system memory interface operating frequency (133 MHz @ 266 MHz CPU).
17. Limited by minimum CPU operating frequency (100 MHz).
18. Limited by minimum memory bus frequency (50 MHz).
19. PCI_SYNC_IN range for this PLL_CFG[0:4] setting does not exist on the MPC8240 and may not be fully
backwards-compatible.
20. No longer supported.
Table 19. PLL Configurations (266-MHz Parts) (continued)
Ref 2
PLL_
CFG[0:4] 10,13
266-MHz Part 9
Multipliers
PCI Clock Input
(PCI_SYNC_IN)
Range 1
(MHz)
Periph Logic/
Mem Bus
Clock Range
(MHz)
CPU Clock
Range
(MHz)
PCI-to-
Mem
(Mem VCO)
Mem-to-
CPU
(CPU VCO)
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