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Communication Processor Module
MOTOROLA
MPC823 USER’S MANUAL
16-139
SERIAL
I/F
COMMUNICATION
16
PROCESSOR
MODULE
16.7.5.6.1 SIRP Indication When RDM = 00. 64 entries cannot be signified with a single
5-bit pointer, two 5-bit pointers are used instead—one for the first 32 entries and one for the
second 32 entries. If the corresponding VTx or VRx bit is set, then:
RAPTR1 and RAPTR2 contain the address of the currently active RX RAM entry. When
the serial interface services entries 1–32, RAPTR1 is incremented and RAPTR2 is
continuously cleared. When the serial interface services entries 33–64, RAPTR1 is
continuously cleared and RAPTR2 is incremented.
TAPTR1 and TAPTR2 contain the address of the currently active TX RAM entry. When
the serial interface services entries 1–32, TAPTR1 is incremented and TAPTR2 is
continuously cleared. When the serial interface services entries 33–64, TAPTR1 is
continuously cleared and TAPTR2 is incremented.
16.7.5.6.2 SIRP Indication When RDM = 01. For the receiver, either RAPTR1 or RAPTR2
is used, depending on the portion of the serial interface RX RAM that is currently active. For
the transmitter, either TAPTR1 or TAPTR2 is used, depending on the portion of the serial
interface TX RAM that is currently active. If the corresponding VTx or VRx bit is set, then:
RAPTR1 contains the address of the currently active RX RAM entry. The serial
interface RAM receive address block that is used is 0–63 and CRORA = 0 in the SISTR.
RAPTR2 contains the address of the currently active RX RAM entry. The serial
interface RAM receive address block that is used is 64–127 and CRORA = 1 in the
SISTR.
TAPTR1 contains the address of the currently active TX RAM entry. The serial interface
RAM transmit address block that is used is 128–191 and CROTA = 0 in the SISTR.
TAPTR2 contains the address of the currently active TX RAM entry. The serial interface
RAM transmit address block that is used is 192–255 and CROTA = 1 in the SISTR.
16.7.6 IDL Interface Operation
The full-duplex ISDN interchip digital link (IDL) interface is used to connect a physical layer
device to the MPC823. The basic and primary rate of the IDL bus is supported by the
MPC823. In the basic rate of IDL, data on three channels (B1, B2, and D) is transferred in a
20-bit frame, providing 160kbps full-duplex bandwidth. The MPC823 is an IDL slave device
that is clocked by the IDL bus master (physical layer device) and has separate receive and
transmit sections. The MPC823 supports one IDL bus as illustrated in
Figure 16-56.