
MOTOROLA
MPC823e Mobile Computing Microprocessor
For More Information On This Product,
Go to: www.freescale.com
7
Architecture
The MPC823e microprocessor uses a dual-processor architecture design approach with large data
and instruction caches to provide high-performance using a general-purpose RISC integer
processor and a special-purpose 32-bit scalar RISC communication processor module. The
peripherals are uniquely designed for communication requirements and can provide embedded
signal processing functions for communication and user interface enhancements and the I/O
support needed for high-speed digital communication.
The MPC823e is comprised of four main modules that interface with the 32-bit internal bus:
The embedded PowerPC core
The system interface unit
The communication processor module
LCD controller
32-BIT RISC MICROCONTROLLER
AND PROGRAM ROM
INSTRUCTION
BUS
MMU
INSTRUCTION
16K
INSTRUCTION
CACHE
MMU
DATA
8K
DATA CACHE
LOAD / STORE
BUS
GENERAL
PURPOSE I/O
INTERRUPT
CONTROLLER
FOUR
TIMERS
TIMER
DUAL-PORT
RAM
MAC
GENERATORS
BAUD RATE
VIRTUAL SERIAL
AND
INDEPENDENT
DMA CHANNELS
LCD AND VIDEO
CONTROLLERS
PCMCIA INTERFACE
REAL-TIME CLOCK
SYSTEM FUNCTIONS
MEMORY CONTROLLER
INTERNAL
BIU
EXTERNAL
BIU
SYSTEM INTERFACE UNIT
USB
SCC2
SPI
I
2
C
SMC1
SMC2
SERIAL INTERFACE
TIME SLOT ASSIGNERS
8K
POWERPC
CORE
SCC3
F
Freescale Semiconductor, Inc.
n
.