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參數(shù)資料
| 型號： | MPC755CVT350LE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 53/56頁 |
| 文件大小： | 0K |
| 描述： | MCU HIP4DP 350MHZ 360-PBGA |
| 標準包裝： | 44 |
| 系列： | MPC7xx |
| 處理器類型： | 32-位 MPC7xx PowerPC |
| 速度： | 350MHz |
| 電壓： | 2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 360-BBGA，F(xiàn)CCBGA |
| 供應商設備封裝： | 360-FCCBGA（25x25） |
| 包裝： | 托盤 |
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MPC755 RISC Microprocessor Hardware Specifications, Rev. 8
6
Freescale Semiconductor
Electrical and Thermal Characteristics
Packages
MPC745: Surface mount 255 plastic ball grid array (PBGA)
MPC755: Surface mount 360 ceramic ball grid array (CBGA)
Surface mount 360 plastic ball grid array (PBGA)
Core power supply
2.0 V ± 100 mV DC (nominal; some parts support core voltages down to
1.8 V; see Table 3 for recommended operating conditions)
I/O power supply
2.5 V ± 100 mV DC or
3.3 V ± 165 mV DC (input thresholds are configuration pin selectable)
4
Electrical and Thermal Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC755.
4.1
DC Electrical Characteristics
Table 1 through Table 7 describe the MPC755 DC electrical characteristics. Table 1 provides the absolute
maximum ratings.
Table 1. Absolute Maximum Ratings1
Characteristic
Symbol
Maximum Value
Unit
Notes
Core supply voltage
VDD
–0.3 to 2.5
V
4
PLL supply voltage
AVDD
–0.3 to 2.5
V
4
L2 DLL supply voltage
L2AVDD
–0.3 to 2.5
V
4
Processor bus supply voltage
OVDD
–0.3 to 3.6
V
3
L2 bus supply voltage
L2OVDD
–0.3 to 3.6
V
3
Input voltage
Processor bus
Vin
–0.3 to OVDD + 0.3 V
V
2, 5
L2 bus
Vin
–0.3 to L2OVDD + 0.3 V
V
2, 5
JTAG signals
Vin
–0.3 to 3.6
V
Storage temperature range
Tstg
–55 to 150
°C
Notes:
1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: Vin must not exceed OVDD or L2OVDD by more than 0.3 V at any time including during power-on reset.
3. Caution: L2OVDD/OVDD must not exceed VDD/AVDD/L2AVDD by more than 1.6 V during normal operation. During power-on
reset and power-down sequences, L2OVDD/OVDD may exceed VDD/AVDD/L2AVDD by up to 3.3 V for up to 20 ms, or by 2.5 V
for up to 40 ms. Excursions beyond 3.3 V or 40 ms are not supported.
4. Caution: VDD/AVDD/L2AVDD must not exceed L2OVDD/OVDD by more than 0.4 V during normal operation. During power-on
reset and power-down sequences, VDD/AVDD/L2AVDD may exceed L2OVDD/OVDD by up to 1.0 V for up to 20 ms, or by 0.7 V
for up to 40 ms. Excursions beyond 1.0 V or 40 ms are not supported.
5. This is a DC specifications only. Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
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