參數資料
型號: MPC755BRX450LE
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 450 MHz, RISC PROCESSOR, CBGA360
封裝: 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁數: 2/52頁
文件大小: 1278K
代理商: MPC755BRX450LE
10
MPC755 RISC Microprocessor Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Table 6 provides the DC electrical characteristics for the MPC755.
Table 7 provides the power consumption for the MPC755.
Table 6. DC Electrical Specifications
At recommended operating conditions (see Table 3)
Characteristic
Nominal
Bus
Voltage 1
Symbol
Min
Max
Unit
Notes
Input high voltage (all inputs except
SYSCLK)
2.5
VIH
1.6
(L2)OVDD + 0.3
V
2, 3
3.3
VIH
2.0
(L2)OVDD + 0.3
V
2, 3
Input low voltage (all inputs except
SYSCLK)
2.5
VIL
–0.3
0.6
V
2
3.3
VIL
–0.3
0.8
V
SYSCLK input high voltage
2.5
KVIH
1.8
OVDD + 0.3
V
3.3
KVIH
2.4
OVDD + 0.3
V
SYSCLK input low voltage
2.5
KVIL
–0.3
0.4
V
3.3
KVIL
–0.3
0.4
V
Input leakage current,
Vin = L2OVDD/OVDD
Iin
—10
A
2, 3
Hi-Z (off-state) leakage current,
Vin = L2OVDD/OVDD
ITSI
—10
A
2, 3, 5
Output high voltage, IOH = –6 mA
2.5
VOH
1.7
V
3.3
VOH
2.4
V
Output low voltage, IOL = 6 mA
2.5
VOL
—0.45
V
3.3
VOL
—0.4
V
Capacitance, Vin = 0 V, f = 1 MHz
Cin
5.0
pF
3, 4
Notes:
1. Nominal voltages; see Table 3 for recommended operating conditions.
2. For processor bus signals, the reference is OVDD while L2OVDD is the reference for the L2 bus signals.
3. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and IEEE 1149.1 boundary scan (JTAG)
signals.
4. Capacitance is periodically sampled rather than 100% tested.
5. The leakage is measured for nominal OVDD and VDD, or both OVDD and VDD must vary in the same direction (for
example, both OVDD and VDD vary by either +5% or –5%).
Table 7. Power Consumption for MPC755
Processor (CPU) Frequency
Unit
Notes
300 MHz
350 MHz
400 MHz
450 MHz
Full-Power Mode
Typical
3.1
3.6
4.0
4.6
W
1, 3
Maximum
4.5
5.3
6.0
8.0
W
1, 2
Doze Mode
Maximum
1.8
2.0
2.3
2.8
W
1, 2
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