- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45353 > MPC740PRX300RE (FREESCALE SEMICONDUCTOR INC) 32-BIT, 300 MHz, RISC PROCESSOR, CBGA255 PDF資料下載
參數(shù)資料
| 型號： | MPC740PRX300RE |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 543K |
| 代理商： | MPC740PRX300RE |
12
XPC750P RISC Microprocessor Hardware Specications
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Figure 5. provides the output timing diagram for the XPC750P.
Figure 5. Output Timing Diagram
1.4.2.4 L2 Clock AC Specications
The L2CLK frequency is programmed by the L2 Conguration Register (L2CR[4:6]) core-to-L2 divisor
ratio. See Table 15. for example core and L2 frequencies at various divisors. Table 11. provides the potential
range of L2CLK output AC timing specications as dened in Figure 6..
The minimum L2CLK frequency of Table 11. is specied by the maximum delay of the internal DLL. The
variable-tap DLL introduces up to a full clock period delay in the L2CLKOUTA, L2CLKOUTB, and
L2SYNC_OUT signals so that the returning L2SYNC_IN signal is phase aligned with the next core clock
(divided by the L2 divisor ratio). Do not choose a core-to-L2 divisor which results in an L2 frequency below
this minimum, or the L2CLKOUT signals provided for SRAM clocking will not be phase aligned with the
XPC750P core clock at the SRAMs.
The maximum L2CLK frequency shown in Table 11. is the core frequency divided by one. Very few L2
SRAM designs will be able to operate in this mode. Most designs will select a greater core-to-L2 divisor to
provide a longer L2CLK period for read and write access to the L2 SRAMs. The maximum L2CLK
frequency for any application of the XPC750P will be a function of the AC timings of the XPC750P, the AC
timings for the SRAM, bus loading, and printed circuit board trace length.
Motorola is similarly limited by system constraints and cannot perform tests of the L2 interface on a
socketed part on a functional tester at the maximum frequencies of Table 11.. Therefore functional operation
and AC timing information are tested at core-to-L2 divisors of 2 or greater.
L2 input and output signals are latched or enabled respectively by the internal L2CLK (which is SYSCLK
SYSCLK
12
15
16
ALL OUTPUTS
TS
ARTRY
ABB, DBB
VM
VM = Midpoint Voltage (1.4V)
15
VM
18
14
13
17
21
19
20
(Except TS, ABB,
ARTRY, DBB)
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關PDF資料 |
PDF描述 |
|---|---|
| MPC740PRX366LE | 32-BIT, 366 MHz, RISC PROCESSOR, CBGA255 |
| MPC740PRX333LE | 32-BIT, 333 MHz, RISC PROCESSOR, CBGA255 |
| MPC755BRX300LX | 32-BIT, 300 MHz, RISC PROCESSOR, CBGA360 |
| MPC745BPX400LX | 32-BIT, 400 MHz, RISC PROCESSOR, PBGA255 |
| MPC755BPX300LX | 32-BIT, 300 MHz, RISC PROCESSOR, PBGA360 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC7410 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:RISC Microprocessor Hardware Specifications Addendum |
| MPC7410_1 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:RISC Microprocessor Hardware Specifications |
| MPC7410_10 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:RISC Microprocessor Hardware Specifications Addendum |
| MPC74-103J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Metal Plate Cement Resistors |
| MPC74-103K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Metal Plate Cement Resistors |
發(fā)布緊急采購，3分鐘左右您將得到回復。