
The MPC7400 PowerPC microprocessor is a high-performance, low-power, 32-bit implementation of the PowerPC
Reduced Instruction Set Computer (RISC) architecture combined with a full 128-bit implementation of Motorola’s
AltiVec technology instruction set, creating a high-performance RISC microprocessor ideal for leading-edge
computing, control, and signal processing functions. The MPC7400 supports the high-bandwidth MPX bus with
minimized signal setup times and reduced idle cycles to increase maximum operating frequency to over 100 MHz,
increased address bus bandwidth, increased data bus bandwidth, and more enhancements. To maintain backward
compatibility for existing applications, the MPC7400 also supports the 60x bus protocol. MPC7400 microprocessors
offer single-cycle double-precision floating-point performance, provide full symmetric multiprocessing (SMP)
capabilities, and support up to 2MB of backside L2 cache. While the
MPC7400 is software-compatible with existing applications for
PowerPC 603e, PowerPC 740, and PowerPC 750
microprocessors, to utilize the full potential of this AltiVec
technology-enabled device, some instruction changes in existing source
code are required to interface with the vector execution unit.
Superscalar Microprocessor
MPC7400 microprocessors feature a high-frequency superscalar
PowerPC core, capable of issuing three instructions per clock cycle
(two instructions + branch) into seven independent execution units:
I
Two integer units
I
Double-precision floating-point unit
I
Vector unit
I
Load/store unit
I
System unit
I
Branch processing unit
AltiVec Technology
Motorola’s AltiVec technology expands the capabilities of
PowerPC microprocessors by providing leading-edge,
general-purpose processing performance while
concurrently addressing high-bandwidth data processing
and algorithmic-intensive computations in a single-chip
solution. AltiVec technology:
I
Meets the computational demands of networking
infrastructure such as multichannel modems, echo
cancellation equipment, and basestation processing.
I
Enables faster, more secure encryption methods
optimized for the SIMD processing model
I
Provides compelling performance for multimedia-
oriented desktop computers, desktop publishing, and
digital video processing
I
Enables real-time processing of the most demanding
data streams (MPEG-2 encode, continuous speech recognition, real-time high-resolution 3D graphics, etc.)
64b Data
32b Address
Bus Interface Unit
60x/MPX Bus
FSRAM
I MMU
Load/Store Unit
Instruction Cache
D MMU
Data Cache
Dispatch
Unit
Completion
Unit
Branch
Unit
64b L2
Cache Port
L2 Tags
Integer
Unit
Integer
Reg File
Floating
Point Unit
Floating Point
Reg File
Vector
Unit
Vector
Reg File
MPC7400FACT/D
Rev. 1
M OTOROLA MPC7400
P OWER PC M ICROPROCESSORS
MPC7400 Microprocessor
Motorola MPC7400 Block Diagram
Fact Sheet