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參數(shù)資料
| 型號： | MPC603RRX200TC |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 30/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 200MHZ 255-CBGA |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | MPC6xx |
| 處理器類型： | 32-位 MPC603e PowerPC |
| 速度： | 200MHz |
| 電壓： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 255-BCBGA，F(xiàn)CCBGA |
| 供應(yīng)商設(shè)備封裝： | 255-FCCBGA（21x21） |
| 包裝： | 托盤 |
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PID7t-603e Hardware Specifications, Rev. 5
8
Freescale Semiconductor
Electrical and Thermal Characteristics
This figure provides the SYSCLK input timing diagram.
Figure 1. SYSCLK Input Timing Diagram
4.2.2
Input AC Specifications
This table provides the input AC timing specifications for the PID7t-603e as defined in Figure 2 and
SYSCLK jitter
—
±150
—
±150
—
±150
—
±150
ps
4
PID7t internal PLL-relock time
—
100
—
100
—
100
—
100
s3, 5
Note:
1. Caution: The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the resulting SYSCLK (bus)
frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0–3] signal description in Section 8, “System Design Information,” for valid
PLL_CFG[0–3] settings.
2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. Cycle-to-cycle jitter, and is guaranteed by design. The total input jitter (short term and long term combined) must be under
±150 ps to guarantee the input/output timing of Section 4.2.2, “Input AC Specifications,” and Section 4.2.3, “Output AC
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum time required
for PLL lock after a stable Vdd, OVdd, AVdd, and SYSCLK are reached during the power-on reset sequence. This specification
also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must
be held asserted for a minimum of 255 bus clocks after the PLL-relock time (100
s) during the power-on reset sequence.
6. Operation below 150 MHz is supported only by PLL_CFG[0–3] = 0b0101. Refer to Section 8.1, “PLL Configuration” for
additional information.
Table 7. Clock AC Timing Specifications (continued)
Vdd = AVdd = 2.5 ± 5% V dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 Tj 105 °C
Num
Characteristic
200 MHz
PBGA
200 MHz
CBGA
266 MHz
CBGA
300 MHz
CBGA
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
VM
CVil
CVih
SYSCLK
2
3
4
VM = Midpoint Voltage (1.4 V)
4
1
VM
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