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參數(shù)資料
| 型號(hào)： | MPC603EFEX266LX |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, CQFP240 |
| 封裝： | 32 X 32 MM, 0.50 MM PITCH, CERAMIC, QFP-240 |
| 文件頁數(shù)： | 29/32頁 |
| 文件大?。?/td> | 498K |
| 代理商： | MPC603EFEX266LX |
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6
PID6-603e Hardware Specifications, Rev 2
Table 5 provides the power consumption for the 603e.
Capacitance, Vin = 0 V, f = 1 MHz (excludes TS, ABB, DBB,
and ARTRY)
Cin
—
10.0
pF
2
Capacitance, Vin = 0 V, f = 1 MHz (for TS, ABB, DBB, and
ARTRY)
Cin
—
15.0
pF
2
Notes:
1. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and JTAG signals.
2. Capacitance is periodically sampled rather than 100% tested.
Table 5. Power Consumption
At recommended operating conditions. See Table 2.
CPU Clock:
SYSCLK
Processor (CPU) Frequency
Unit
Notes
100 MHz
133.33 MHz
Full-On Mode (DPM Enabled)
Typical
Max.
3.2
4.2
W
1, 3
4.0
5.3
W
1, 2
Doze Mode
Typical
1.0
1.3
W
1, 2
Nap Mode
Typical
70
85
mW
1, 2
Sleep Mode
Typical
40
50
mW
1, 2
Sleep Mode—PLL Disabled
Typical
5
6
mW
1, 2
Sleep Mode—PLL and SYSCLK Disabled
Typical
3
mW
1, 2
Notes:
1. These values apply for all valid bus ratios (PLL_CFG[0–3] settings). The
values do not include I/O supply power (OVdd) or PLL supply power
(AVdd). OVdd power is system dependent, but is typically <10% of Vdd
power. Worst-case power consumption for AVdd = 15 mw.
2. Maximum power is measured at Vdd = 3.465 V using a worst-case
instruction mix.
3. Typical power is an average value measured at Vdd = AVdd = OVdd = 3.3
V in a system executing typical applications and benchmark sequences
Table 4. DC Electrical Specifications (Continued)
At recommended operating conditions. See Table 2.
Characteristic
Symbol
Min
Max
Unit
Notes
F
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sc
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le
S
e
m
ic
o
n
d
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to
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I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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