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參數(shù)資料
| 型號： | MPC566AZP56 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 56 MHz, RISC MICROCONTROLLER, PBGA388 |
| 封裝： | 27 X 27 MM, 2.55 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-388 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 139K |
| 代理商： | MPC566AZP56 |
MPC565/MPC566
PRODUCT BRIEF
MOTOROLA
2
IEEE 1149.1 JTAG test access port
Bus supports multiple master designs
Flexible memory protection units in BBC (IMPU) and L2U (DMPU)
Flexible chip selects via memory controller
— 24-bit address and 32-bit data buses
— Four- to 16-Mbyte (data) or 4-Gbyte (instruction) region size support
— Four-beat transfer bursts, two-clock minimum bus transactions
— Use with SRAM, EPROM, flash and other peripherals
— Byte selects or write enables
— 32-bit address decodes with bit masks
— Four instruction regions
— Four data regions
Default attributes available in one global entry
Attribute support for speculative accesses
Exception vector table relocation features allow exception table to be relocated to following loca-
tions:
— 0x0000 0100 (normal MPC5xx exception table location)
— 0x0001 0000 (0 + 64 Kbytes; second page of internal flash)
— Second internal flash module
— Internal SRAM
— 0x0FFF_0100 (external memory space; normal MPC5xx exception table location)
USIU supports dual-mapping of flash to move part of internal flash memory to external bus for de-
velopment
One Mbyte Flash
Two UC3F modules, 512 Kbytes each
Page mode read
Block (64-Kbyte) erasable
External 4.75- to 5.25-V VPP program, erase, and read power supply
36-Kbyte Static RAM (CALRAM)
Composed of four- and 32-Kbyte CALRAM modules
Fast access: one clock
Keep-alive power
Soft defect detection (SDD)
4-Kbyte calibration (overlay) RAM per module (eight Kbytes total)
Eight 512-byte overlay regions per module (16 regions total)
IEEE – ISTO Nexus 5001-1999 Debug Port (Class 3)
Address (24) and data (32) pins can be used as GPIO in single chip mode
Reduced-port mode (1 MDI, 2 MDo) or full-port mode (2 MDI. 8 MDO)
Many peripheral pins can be used as GPIO when not used as primary functions
5-V outputs with slew rate control
Integrated I/O System
True 5-V I/O
Three time processing units (TPU3)
— 16 channels each
— Each TPU3 is a microcoded timer subsystem
— One 6-Kbyte and one 4-Kbyte dual port TPU RAM (DPTRAM), one (6-Kbyte) shared by two
TPU3 modules for TPU microcode and the 4-Kbyte dedicated to the third TPU3 for microcode.
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