
QADC64E Legacy Mode Operation
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
13-53
Figure 13-26. Bus Cycle Accesses
Byte access to an even address of a QADC64E location is shown in the top illustration of
Figure 13-26. In
the case of write cycles, byte 1 of the register is not disturbed. In the case of a read cycle, the QADC64E
provides both byte 0 and byte 1.
Byte access to an odd address of a QADC64E location is shown in the center illustration of
Figure 13-26.
In the case of write cycles, byte 0 of the register is not disturbed. In the case of read cycles, the QADC64E
provides both byte 0 and byte 1.
16-bit accesses to an even address read or write byte 0 and byte 1 as shown in the lowest illustration of
Figure 13-26. The full 16 bits of data is written to and read from the QADC64E location with each access.
16-bit accesses to an odd address require two bus cycles; one byte of two different 16-bit QADC64E
locations is accessed. The first bus cycle is treated by the QADC64E as an 8-bit read or write of an odd
address. The second cycle is an 8-bit read or write of an even address. The QADC64E address space is
organized into 16-bit even address locations, so a 16-bit read or write of an odd address obtains or provides
the lower half of one QADC64E location, and the upper half of the following QADC64E location.
QADC64E Bus CYC ACC
Intermodule Bus
8-bit Access of an Even Address (ISIZ = 01, A0 = 0)
Byte 0
Byte 1
Byte 0
Byte 1
QADC Location
WR
Intermodule Bus
8-bit Access of an Odd Address (ISIZ = 01, A0 = 1; OR ISIZ = 10, A0 = 1)
Byte 0
Byte 1
Byte 0
Byte 1
QADC Location
WR
Intermodule Bus
16-Bit Aligned Access (ISIZ = 10, A0 = 0)
BYTE 0
BYTE 1
BYTE 0
BYTE 1
QADC Location
WR