
MOTOROLA
Chapter 3. Central Processing Unit
3-19
User Instruction Set Architecture (UISA) Register Set
3.7.4.3
Condition Register CRn Field — Compare Instruction
When a specified CR field is set by a compare instruction, the bits of the specified field are
interpreted as shown in
Table 3-9. A condition register field can also be accessed by the
mfcr, mcrf, and mtcrf instructions.
3.7.5
Integer Exception Register (XER)
The integer exception register (XER), SPR 1, is a user-level, 32-bit register.
Table 3-8. Bit Settings for CR1 Field of CR
CR1 Bit
Description
0
Floating-point exception (FX). This is a copy of the final state of FPSCR[FX] at the completion of the
instruction.
1
Floating-point enabled exception (FEX).This is a copy of the final state of FPSCR[FEX] at the completion of
the instruction.
2
Floating-point invalid exception (VX).This is a copy of the final state of FPSCR[VX] at the completion of the
instruction.
3
Floating-point overflow exception (OX).This is a copy of the final state of FPSCR[OX] at the completion of
the instruction.
Table 3-9. CRn Field Bit Settings for Compare Instructions
CRn Bit 1
1 Here, the bit indicates the bit number in any one of the four-bit subfields, CR0–CR7
Description
0
Less than, floating-point less than (LT, FL).
For integer compare instructions, (rA) < SIMM, UIMM, or (rB) (algebraic comparison) or (rA) SIMM, UIMM,
or (rB) (logical comparison). For floating-point compare instructions, (frA) < (frB).
1
Greater than, floating-point greater than (GT, FG).
For integer compare instructions, (rA) > SIMM, UIMM, or (rB) (algebraic comparison) or (rA) SIMM, UIMM,
or (rB) (logical comparison). For floating-point compare instructions, (frA) > (frB).
2
Equal, floating-point equal (EQ, FE).
For integer compare instructions, (rA) = SIMM, UIMM, or (rB).
For floating-point compare instructions, (frA) = (frB).
3
Summary overflow, floating-point unordered (SO, FU).
For integer compare instructions, this is a copy of the final state of XER[SO] at the completion of the
instruction. For floating-point compare instructions, one or both of (frA) and (frB) is not a number (NaN).
MSB
0
1
2
3
4
5
6
7
8
9 10 11 1213141516171819202122232425 26 27 28 29 30
LSB
31
Field SO
OV CA
—
BYTES
Reset
Unchanged
00_0000_0000_0000_0000_0
Unchanged
Addr
SPR 1
Figure 3-8. Integer Exception Register (XER)