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MOTOROLA
Chapter 4. Burst Buffer Controller 2 Module
4-15
Branch Target Buffer
DECRAM can be accessed from the U-bus and cannot be accessed by the ICDU logic.
In this mode:
The DECRAM supports word, half-word and byte operations.
The DECRAM is emulated to be 32 bits wide. For example: a load access from
offset 0 in the DECRAM will deliver the concatenation of the first word in each of
the DECRAM banks when RAM 1 contains the 16 LSB of the word and RAM 2
contains the 16 MSB.
Load accesses at any width are supplied with 32 bits of valid data.
The DECRAM communicates with the U-bus pipeline but does not support
pipelined accesses to itself. If a store operation is second in the U-bus pipe, the store
is carried out immediately and the U-bus acknowledgment is performed when the
previous transaction in the pipe completes.
Burst access is not supported.
NOTE
Instructions running from the DECRAM should not also
perform store operations to the DECRAM.
4.4.1.1
Memory Protection Violations
The DECRAM module does not acknowledge U-bus accesses that violate the configuration
defined in the
BBCMCR. This causes the machine check exception for the internal RCPU
or an error condition for the MPC561/MPC563 external master.
4.4.1.2
DECRAM Standby Operation Mode
The bus interface and DECRAM control logic are powered by VDD supply. The memory
array is supplied by a separate power pin (IRAMSTBY).
4.5
Branch Target Buffer
The burst buffer controller contains a branch target buffer (BTB) to reduce the impact of
branches on processor performance. Following is a summary of the BTB features:
Software controlled BTB enable/disable, inhibit, and invalidate
User transparent — no user management required
The BTB consists of eight branch target entries (BTE). Refer to
Figure 4-5. All entries are
managed as a fully associative cache. Each entry contains a tag and several data buffers
related to this tag.