
13-8
MPC561/MPC563 Reference Manual
MOTOROLA
Programming the QADC64E Registers
The CCW table follows the register block in the address map. There are 64 table entries to
hold the desired analog conversion sequences. Each CCW table entry is 16-bits, with ten
implemented bits in four fields.
The final block of address space belongs to the result word table, which appears in three
places in the memory map. Each result word table location holds one 10-bit conversion
value.
13.3.1
QADC64E Module Configuration Register (QADMCR)
The QADCMCR contains five implemented bits that control the operating modes of the
QADC64E module. The configurable modes are freeze, stop and supervisor. The
QADCMCR also implements a pair of bits that together select either legacy or enhanced
mode for the QADC module, and lock that operating mode.
.
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LSB
15
Field STOP FRZ
—
LOCK FLIP SUPV
—
SRESET
0000_0000
1
000_0000
Addr
0x30 4800 (QADCMCR_A); 0x30 4C00 (QADCMCR_B)
Figure 13-4. Module Configuration Register (QADCMCR)
Table 13-5. QADCMCR Bit Descriptions
Bits
Name
Description
0
STOP
0 = Disable stop mode
1 = Enable stop mode
1
FRZ
0 = Ignores the IMB3 internal FREEZE signal
1 = Finish any conversion in progress, then freeze
2:5
—
Reserved
6
LOCK
Lock/Unlock QADC Mode of operation as defined by FLIP bit. Refer to
Section 13.3.1.3,0 = QADC mode is locked
1 = QADC mode is unlocked and changeable using FLIP bit
7
FLIP
QADC Mode of Operation – The FLIP bit allows selection of the mode of operation of the QADC
module, either legacy mode (default) or enhanced mode. This bit can only be written when the
0 = Legacy mode enabled
1 = Enhanced mode enabled