
17-18
MPC561/MPC563 Reference Manual
MOTOROLA
MIOS14 Counter Prescaler Submodule (MCPSM)
17.7.3.2 MCPSM Status/Control Register (MCPSMSCR)
NOTE
If the binary value 0b0001 is entered in PSL[3:0], the output
signal is stuck at zero, no clock is output.
MSB
0
1
2345
6789
10
11
12
13
14
LSB
15
Field PREN FREN
—
PSL3:0
SRESET
0000_0000_0000_0000
Addr
0x30 6816
Figure 17-9. MCPSM Status/Control Register (MCPSMSCR)
Table 17-7. MCPSMSCR Bit Descriptions
Bits
Name
Description
0
PREN
Prescaler enable bit — This active high read/write control bit enables the MCPSM counter. The
PREN bit is cleared by reset.
0 MCPSM counter disabled.
1 MCPSM counter enabled.
1
FREN
Freeze bit — This active high read/write control bit when set make possible a freeze of the
MCPSM counter if the MIOB freeze line is activated. NOTE: This line is active when
MIOS14MCR[STOP] is set or when MIOS14MCR[FREN] and the IMB3 FREEZE line are set.
When the MCPSM is frozen, it stops counting. Then when the FREN bit is reset or when the
freeze condition on the MIOB is negated, the counter restarts from where it was before freeze.
The FREN bit is cleared by reset.
0 MCPSM counter not frozen.
1 MCPSM counter frozen if MIOB freeze active.
2:11
—
Reserved
12:15
PSL[3:0]
Clock prescaler — This 4-bit read/write data register stores the modulus value for loading into the
clock prescaler. The new value is loaded into the counter on the next time the counter equals one
or when disabled (PREN =0).
Table 17-8. Clock Prescaler Setting
PSL[3:0] Value
Divide Ratio
Hex
Binary
0x0
0b0000
16
0x1
0b0001
No counter clock output
0x2
0b0010
2
0x3
0b0011
3
...
0xE
0b1110
14
0xF
0b1111
15