參數(shù)資料
型號(hào)： MPC561CVR40
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 2/2頁(yè)
文件大?。?/td> 0K
描述： IC MPU 32BIT 40MHZ 388-PBGA
標(biāo)準(zhǔn)包裝： 40
系列： MPC5xx
核心處理器： PowerPC
芯體尺寸： 32-位
速度： 40MHz
連通性： CAN，EBI/EMI，SCI，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 64
程序存儲(chǔ)器類(lèi)型： ROMless
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 2.5 V ~ 2.7 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 32x10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 388-BBGA
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 732 (CN2011-ZH PDF)
配用： MPC564EVB-ND - KIT EVAL FOR MPC561/562/563/564
MPC561FACT/D
40 or 56 MHz operation
IRAMSTBY voltage regu-
lator permits retention
of SRAM data in low
power mode
Available in both indus-
trial temperature (-40° C
to +85° C) and automo-
tive temperature ranges
(-40° C to +125° C)
Four low power modes:
On, doze, sleep, deep
sleep, and power-down
JTAG
BDM
USIU
TPU3
8K DPTRAM
PPM
QADC
MIOS14
TOUCAN
BBC2 /
DECRAM
TOUCAN
UMB
QSMCM
FPU
PPC CORE
16K
RAM
4K
RAM
CALBIU
READI
L2U
TPU3
QADC
12K
RAM
Learn more about the MPC561.
Visit our Web site at:
www.motorola.com/semiconductors
NEXUS debug port (class 3)
– IEEE-ISTO 5001 - 1999
Dual Time Processor
Units (Type 3)
Three TouCAN (CAN
2.0B) controller modules
5V general purpose I/O
Modular I/O Subsystem
(MIOS) module provides
22-timer channels and
16 general purpose I/O
Queued Serial Multi-
Channel Module (QSMCM)
with 1 Queued Serial
Peripheral Interface (QSPI)
and 2 Serial Communi-
cation Interfaces (SCI)
Two enhanced QADC64
modules with legacy mode
support (32 channels)
MOTOROLA MPC561
BENEFITS
Cost-effective perform-
ance for complex appli-
cations not requiring
embedded flash or large
memory arrays
Low development costs
Quick time-to-market
Code capability and
scalability among
family members and
between generations
helps to eliminate
migration worries,
additionally providing
software reuse between
family members.
COMMITTED TO YOU FOR
THE LONG RUN
With 30 years of leadership
in electronics, Motorola
understands your priorities –
design higher performance
products in less time and
at a reduced total cost.
To that end, the MPC500
family of microcontrollers,
including the MPC561,
enables you to buy as
much or as little perform-
ance as you need to
help meet your product
development goals.
MOTOROLA MPC561
FEATURES
MPC500 core with
Floating Point Unit –
compliant with the
PowerPC instruction
set architecture
32K bytes of static RAM
with 8K bytes of DPTRAM
(which can be shared by
TPUs for customized TPU
code) and 2K bytes of
DECRAM available for
additional RAM used for
compression tables on
the compression parts
(MPC562, MPC564 and
MPC566) or otherwise
used as SRAM
F
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Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc., 2004. All rights reserved.
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