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參數(shù)資料
| 型號： | MPC5607BCLU4R |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | FLASH, 48 MHz, MICROCONTROLLER, PQFP176 |
| 封裝： | 24 X 24 MM, 0.50 MM PITCH, LQFP-176 |
| 文件頁數(shù)： | 83/106頁 |
| 文件大?。?/td> | 667K |
| 代理商： | MPC5607BCLU4R |
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MPC5607B Microcontroller Data Sheet, Rev. 5
Electrical characteristics
Freescale Semiconductor
78
IINJ
SR — Input current Injection
Current
injection on
one ADC_1
input, different
from the
converted one
VDD = 3.3 V ± 10%
–5
—
5
mA
VDD = 5.0 V ± 10%
–5
—
5
INLP
CC T Absolute Integral
non-linearity-Precise channels
No overload
—
1
3
LSB
INLX
CC T Absolute Integral
non-linearity-Extended
channels
No overload
—
1.5
5
LSB
DNL
CC T Absolute Differential
non-linearity
No overload
—
0.5
1
LSB
OFS
CC T Absolute Offset error
——
2
—
LSB
GNE
CC T Absolute Gain error
——
2
—
LSB
TUEP7
CC P Total Unadjusted Error for
precise channels, input only
pins
Without current injection
–6
—
6
LSB
T
With current injection
–8
—
8
TUEX7
CC T Total Unadjusted Error for
extended channel
Without current injection
–10
—
10
LSB
T
With current injection
–12
—
12
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified
2 Analog and digital V
SS must be common (to be tied together externally).
3 V
AINx may exceed VSS_ADC1 and VDD_ADC1 limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0xFFF.
4 During the sample time the input capacitance C
S can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC1_S. After the end
of the sample time tADC1_S, changes of the analog input voltage have no effect on the conversion result. Values for the
sample clock tADC1_S depend on programming.
5 This parameter does not include the sample time t
ADC1_S, but only the time for determining the digital result and the
time to load the result’s register with the conversion result.
6 Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by
internal divider by 2.
7 Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
Table 42. ADC_1 conversion characteristics (12-bit ADC_1) (continued)
Symbol
C
Parameter
Conditions1
Value
Unit
Min
Typ
Max
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