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參數(shù)資料
| 型號： | MPC5604PEFMLL7 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, MS-026BED, LQFP-100 |
| 文件頁數(shù)： | 25/72頁 |
| 文件大?。?/td> | 1382K |
| 代理商： | MPC5604PEFMLL7 |
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MPC5604P Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
31
3.6
Power Management Electrical Characteristics
3.6.1
Voltage Regulator Electrical Characteristics
The internal voltage regulator requires an external NPN (BCP56 or BCP68) ballast to be connected as shown in Figure 4 as well
as an external capacitance (CREG) to be connected to the device in order to provide a stable low voltage digital supply.
Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to limit the
serial inductance of the board to less than 5 nH.
NOTE
The voltage regulator output cannot be used to drive external circuits. Output pins are to be
used only for decoupling capacitance.
For the MPC5604P microcontroller , 10 F should be placed between each of the three VDD_LV_CORx/VSS_LV_CORx supply
pairs and also between the VDD_LV_REGCOR/VSS_LV_REGCOR pair. Additionally, 40 μF should be placed between the
VDD_HV_REG/VSS_HV_REG pins.
VDD = 3.0 V to 3.6 V / 4.5 V to 5.5 V, TA = –40 to 125 °C, unless otherwise specified.
Figure 4. External NPN Ballast Connections
2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification
Table 12. Voltage Regulator Electrical Characteristics
No.
Symbol
Parameter
Conditions
Min
Max
Unit
1
VDD_LV_REGCOR
P Output voltage under maximum load
run supply current configuration
Post-trimming
1.145
1.4
V
2
CDEC1
SR External decoupling/stability ceramic
capacitor
4 capacitances of 10 F
each
4
× 10
—
F
RREG
ESR of external cap
between 100 kHz and
10 MHz
—
0.2
Ω
3
CDEC2
SR External decoupling/stability ceramic
capacitor on VDD_HV_REG
—
47
—
F
BCTRL
VDD_HV_REG
VDD_LV_REGCOR
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