參數(shù)資料
型號： MPC5603PGF0VLL4R
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT LQFP-100
文件頁數(shù)： 35/82頁
文件大小： 1613K
代理商： MPC5603PGF0VLL4R
MPC5604P Microcontroller Data Sheet, Rev. 6.1
Freescale Semiconductor
40
Table 17. Supply Current (5.0 V, NVUSRO[PAD3V5V]=0)
Symbol
Parameter
Conditions
Value
Unit
Typ
Max
I
DD_LV_CORE
T
Supply
current
RUN - Maximum Mode1
1 Maximum mode: FlexPWM, ADCs, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, 1st and 2nd PLL enabled. I/O supply current
excluded.
V
DD_LV_CORE
externally forced at 1.3 V
40 MHz
62
77
mA
64 MHz
71
88
RUN - Typical Mode2
2 Typical mode configurations: DSPI, LINFlex, FlexCAN, 15 output pins, 1st PLL only. I/O supply current excluded.
40 MHz
45
56
64 MHz
52
65
P
RUN - Maximum Mode3
3 Code fetched from Ram, PLL0: 64 MHz system clock (x4 multiplier with 16MHz XTAL), PLL1 is ON @ PHI_div2 = 120 Mhz
and PHI_div3 = 80 Mhz, auxiliary clock sources set that all peripherals receive maximum frequency, all peripheral enabled.
V
DD_LV_CORE
externally forced at 1.3 V
64 MHz
60
75
HALT Mode4
4 Halt mode configurations: Code fetched from RAM, C & D FLASH in low power mode, OSC/PLL0/PLL1 are OFF, Core clock
frozen, all peripherals are disabled.
V
DD_LV_CORE
externally forced at 1.3 V
—1.5
10
STOP Mode5
5 STOP "P" mode DUT configuration: Code fetched from RAM, C & D FLASH off, OSC/PLL0/PLL1 are OFF, Core clock frozen,
all peripherals are disabled.
VDD_LV_CORE
externally forced at 1.3 V
—1
10
IDD_FLASH
T
FLASH supply current
during read
VDD_HV_FL at 5.0 V
—
10
12
FLASH supply current
during erase operation
on 1 flash module
VDD_HV_FL at 5.0 V
—
15
19
IDD_ADC
T
ADC supply current - Maximum Mode1 VDD_HV_AD0 at 5.0 V
VDD_HV_AD1 at 5.0 V
ADC Freq = 16MHz
ADC16
6 Includes Temperature Sensor current consumption.
3.5
5
ADC0
3
4
ADC supply current - Typical Mode2
ADC16
0.8
1
ADC0
0.005
0.006
I
DD_OSC
T
OSC supply current
VDD_OSC at 5.0 V
8 MHz
2.6
3.2
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