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參數(shù)資料
| 型號： | MPC5603PGF0MLQ6R |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, QFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-144 |
| 文件頁數(shù)： | 38/82頁 |
| 文件大?。?/td> | 1613K |
| 代理商： | MPC5603PGF0MLQ6R |
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MPC5604P Microcontroller Data Sheet, Rev. 6.1
Freescale Semiconductor
43
3.8.4
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as
described in Table 20.
Table 21 provides the weight of concurrent switching I/Os.
In order to ensure device functionality, the sum of the weight of concurrent switching I/Os on a single segment should remain
below the 100%.
3 Code fetched from Ram, PLL0: 64 MHz system clock (x4 multiplier with 16MHz XTAL), PLL1 is ON @ PHI_div2 = 120 Mhz
and PHI_div3 = 80 Mhz, auxiliary clock sources set that all peripherals receive maximum frequency, all peripheral enabled.
4 Halt mode configurations: Code fetched from RAM, C & D FLASH in low power mode, OSC/PLL0/PLL1 are OFF, Core clock
frozen, all peripherals are disabled.
5 STOP "P" mode DUT configuration: Code fetched from RAM, C & D FLASH off, OSC/PLL0/PLL1 are OFF, Core clock frozen,
all peripherals are disabled.
6 Includes Temperature Sensor current consumption.
Table 20. I/O supply segment
Package
Supply segment
12345
67
144 LQFP
pin8 – pin20
pin23 – pin38 pin39 – pin55 pin58 – pin68 pin73 – pin89 pin92 – pin125 pin128 – pin5
100 LQFP
pin15 – pin26 pin27 – pin38 pin41 – pin46 pin51 – pin61 pin64 – pin86 pin89 – pin10
—
Table 21. I/O weight
PAD
144 LQFP
100 LQFP
Weight 5V
Weight 3.3V
Weight 5V
Weight 3.3V
NMI
1%1%1%
1%
PAD[6]
6%
5%
14%
13%
PAD[49]
5%
4%
14%
12%
PAD[84]
14%
10%
—
PAD[85]
9%
7%
—
PAD[86]
9%
6%
—
MODO0
12%
8%
—
PAD[7]
4%
11%
10%
PAD[36]
5%
4%
11%
9%
PAD[8]
5%
4%
10%
9%
PAD[37]
5%
4%
10%
9%
PAD[5]
5%
4%
9%
8%
PAD[39]
5%
4%
9%
8%
PAD[35]
5%
4%
8%
7%
PAD[87]
12%
9%
—
PAD[88]
9%
6%
—
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