參數(shù)資料
型號： MPC5603PGF0MLL4
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 40 MHz, MICROCONTROLLER, QFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT LQFP-100
文件頁數(shù)： 43/82頁
文件大?。?/td> 1613K
代理商： MPC5603PGF0MLL4
MPC5604P Microcontroller Data Sheet, Rev. 6.1
Freescale Semiconductor
48
3.11
FMPLL Electrical Characteristics
Table 26. PLLMRFM Electrical Specifications
(VDDPLL = 3.0 V to 3.6 V, VSS = VSSPLL = 0 V, TA = TL to TH)
Symbol
Parameter
Conditions
Value
Unit
min
max
fref_crystal
fref_ext
D
PLL reference frequency range1
1 Considering operation with PLL not bypassed.
Crystal reference
4
40
MHz
fpll_in
D
Phase detector input frequency range
(after pre-divider)
—4
16
MHz
fFMPLLO
UT
D
Clock frequency range in normal
mode
—
4
120
MHz
fFREE
P
Free running frequency
Measured using
clock division —
typically /16
20
150
MHz
fsys
D
On-chip PLL frequency2
—
16
120
MHz
tCYC
D
System clock period
—
1 / fsys
ns
fLORL
fLORH
D
Loss of reference frequency window2
2 “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked
mode.
Lower limit
1.6
3.7
MHz
Upper limit
24
56
fSCM
D
Self-clocked mode frequency3,4
3 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside
the fLOR window.
4 f
VCO self clock range is 20-150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in
enhanced mode.
—
20
150
MHz
CJITTER
TCLKOUT
period
jitter5,6,7,8
Short-term jitter9
fSYS maximum
-4
4
% fCLKOUT
Long-term jitter (avg.
over 2 ms interval)
fPLLIN = 16 MHz
(resonator)
,
fPLLCLK @ 64
MHz, 4000
cycles
—10
ns
tlpll
D
PLL lock time 10, 11
—
200
μs
tdc
D
Duty cycle of reference
—40
60
%
fLCK
D
Frequency LOCK range
—
-6
6
% fsys
fUL
D
Frequency un-LOCK range
—
-18
18
% fsys
fCS
fDS
D
Modulation Depth
Center spread
±0.25
±4.012
%fsys
Down Spread
-0.5
-8.0
fMOD
D
Modulation frequency13
—
70
kHz
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