參數(shù)資料
型號(hào)： MPC5603PEFMLL7R
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, MS-026BED, LQFP-100
文件頁(yè)數(shù)： 28/72頁(yè)
文件大小： 1382K
代理商： MPC5603PEFMLL7R
MPC5604P Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
34
VHYSR
D RESET, Schmitt trigger
hysteresis
0.1 VDD_HV_IOx
—
V
VOLR
D RESET, low level output voltage IOL =3mA
—
0.1VDD_HV_IOx
V
IPUR
D RESET, equivalent pull-up
current
VIN =VIL
–130
—
A
VIN =VIH
—
–10
1 “SR” parameter values must not exceed the absolute maximum ratings shown in Table 5.
Table 16. Supply Current (5.0 V, NVUSRO[PAD3V5V]=0)
Symbol
Parameter
Conditions
Value1
1 All values to be confirmed after characterization/data collection.
Unit
Typ
Max
I
DD_LV_CORE
T
Supply
current
RUN - Maximum Mode2
2 Maximum mode: FlexPWM, ADCs, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, 1st and 2nd PLL enabled, 125 °C ambient.
I/O supply current excluded.
V
DD_LV_CORE
externally forced at 1.3 V
40 MHz
62
TBD
mA
64 MHz
71
TBD
RUN - Airbag Mode3
3 Airbag mode configurations: DSPI, LINFlex, FlexCAN, 15 output pins, 1st PLL only, 105 °C ambient. I/O supply current
excluded.
40 MHz
45
TBD
64 MHz
52
TBD
P
RUN - Maximum Mode4
4 Code fetched from Ram, PLL0 : 64 MHz system clock (x4 multiplier with 16MHz XTAL), PLL1 : ON @ PHI_div2 = 120 Mhz;
PHI_div3 = 80 Mhz, auxillary clock sources set that all peripherals receive maximum frequency, all peripheral enabled.
V
DD_LV_CORE
externally forced at 1.3 V
64 MHz
60
TBD
HALT Mode5
5 Halt mode configurations: Code fetched from RAM, C & D FLASH in low power mode, OSC/PLL0/PLL1 are OFF, Core clock
frozen, all peripherals are disabled.
V
DD_LV_CORE
externally forced at 1.3 V
—1.5
10
STOP Mode6
VDD_LV_CORE
externally forced at 1.3 V
—1
10
IDD_FLASH
T
FLASH supply current
during read
VDD_HV_FL at 5.0 V
—
10
TBD
FLASH supply current
during erase operation
on 1 flash module
VDD_HV_FL at 5.0 V
—
15
TBD
IDD_ADC
T
ADC supply current - Maximum Mode2 VDD_HV_AD0 at 5.0 V
VDD_HV_AD1 at 5.0 V
ADC Freq = 16MHz
ADC17
4.3
TBD
ADC0
3.5
TBD
ADC supply current - Airbag Mode3
ADC17
0.8
TBD
ADC0
0.005
TBD
I
DD_OSC
T
OSC supply current
VDD_OSC at 5.0 V
8 MHz
2.6
TBD
Table 15. DC Electrical Characteristics (5.0 V, NVUSRO[PAD3V5V]=0) (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
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