參數(shù)資料
型號: MPC5603CF1CLL4
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, LQFP-100
文件頁數(shù): 67/106頁
文件大?。?/td> 1693K
代理商: MPC5603CF1CLL4
Electrical characteristics
MPC5604B/C Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
63
4.12.3.1
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according
to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This
test conforms to the AEC-Q100-002/-003/-011 standard.
4.12.3.2
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance:
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 30. ESD absolute maximum ratings1 2
1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Symbol
C
Ratings
Conditions
Class
Max value
Unit
VESD(HBM) CC T Electrostatic discharge voltage
(Human Body Model)
TA = 25 °C
conforming to AEC-Q100-002
H1C
2000
V
VESD(MM) CC T Electrostatic discharge voltage
(Machine Model)
TA = 25 °C
conforming to AEC-Q100-003
M2
200
VESD(CDM) CC T Electrostatic discharge voltage
(Charged Device Model)
TA = 25 °C
conforming to AEC-Q100-011
C3A
500
750 (corners)
Table 31. Latch-up results
Symbol
C
Parameter
Conditions
Class
LU
CC
T Static latch-up class
TA = 125 °C
conforming to JESD 78
II level A
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