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參數(shù)資料
| 型號： | MPC5602DCLLR |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 48 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-100 |
| 文件頁數(shù)： | 55/77頁 |
| 文件大?。?/td> | 686K |
| 代理商： | MPC5602DCLLR |
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Electrical characteristics
MPC5602D Microcontroller Data Sheet, Rev. 3.1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
59
DNL
CC T Absolute Differential
non-linearity
No overload
—0.5
1
LSB
OFS
CC T Absolute Offset error
—
—2
—
LSB
GNE
CC T Absolute Gain error
—
—2
—
LSB
TUEP7 CC P Total unadjusted error
for precise channels,
input only pins
Without current injection
–6
6
LSB
T
With current injection
–8
8
TUEX7 CC T Total unadjusted error
for extended channel
Without current injection
–10
10
LSB
T
With current injection
–12
12
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2 Analog and digital V
SS must be common (to be tied together externally).
3 V
AINx may exceed VSS_ADC and VDD_ADC limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0xFFF.
4 Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured
by internal divider by 2.
5 During the sample time the input capacitance C
S can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the
end of the sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values
for the sample clock tADC_S depend on programming.
6 This parameter does not include the sample time t
ADC_S, but only the time for determining the digital result and the
time to load the result’s register with the conversion result.
7 Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
Table 38. ADC conversion characteristics (continued)
Symbol
C
Parameter
Conditions1
Value
Unit
Min
Typ
Max
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