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參數(shù)資料
| 型號： | MPC5602CF1CLL4 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, LQFP-100 |
| 文件頁數(shù)： | 88/106頁 |
| 文件大小： | 1693K |
| 代理商： | MPC5602CF1CLL4 |
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MPC560
4B/C
Micr
ocontr
olle
rData
Sheet,
Re
v
.8
Ele
c
trical
cha
rac
te
ristic
s
Fre
e
scale
Semico
nductor
82
11
tSUO
7
CC D Data valid after SCK edge Master mode
—
32
—
50
ns
Slave mode
—
52
—
160
12
tHO
7
CC D Data hold time for outputs
Master mode
0
—
0
—
ns
Slave mode
8
—
13
—
1 Operating conditions: Cout = 10 to 50 pF, Slew
IN = 3.5 to 15 ns.
2 Maximum value is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM. A positive value means that SCK
starts before CSn is asserted. DSPI2 has only SLOW SCK available.
3 Maximum value is reached when CSn pad is configured as MEDIUM pad while SCK pad is configured as SLOW. A positive value means that CSn is
deasserted before SCK. DSPI0 and DSPI1 have only MEDIUM SCK available.
4 The t
CSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay
between internal CS and internal SCK must be higher than
t
CSC to ensure positive tCSCext.
5 The t
ASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay between
internal CS and internal SCK must be higher than
t
ASC to ensure positive tASCext.
6 This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register.
7 SCK and SOUT configured as MEDIUM pad
Table 42. DSPI characteristics1 (continued)
No.
Symbol
C
Parameter
DSPI0/DSPI1
DSPI2
Unit
Min
Typ
Max
Min
Typ
Max
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