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參數(shù)資料
| 型號： | MPC555LFMZP40R2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 2M FLASH 132MHZ 272-PBGA |
| 標準包裝： | 500 |
| 系列： | MPC5xx |
| 核心處理器： | PowerPC |
| 芯體尺寸： | 32-位 |
| 速度： | 40MHz |
| 連通性： | CAN，EBI/EMI，SCI，SPI，UART/USART |
| 外圍設備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 101 |
| 程序存儲器容量： | 448KB（448K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 26K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉換器： | A/D 32x10b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 272-PBGA |
| 包裝： | 帶卷 (TR) |
| 配用： | MPC555CMEE-ND - KIT EVAL FOR MPC555 |
This document provides an overview of the
MPC555 microcontroller, including a block
diagram showing the major modular components and sections that list the major features. The
MPC555 member of the Freescale MPC500 RISC Microcontroller family.
1
Introduction
The MPC555 device offers the following features:
PowerPC core with floating-point unit
26 Kbytes fast RAM and 6 Kbytes TPU microcode RAM
448 Kbytes Flash EEPROM with 5-V programming
5-V I/O system
Serial system: queued serial multi-channel module (QSMCM), dual CAN 2.0B
controller
modules (TouCANTM)
50-channel timer system: dual time processor units (TPU3), modular I/O system
(MIOS1)
32 analog inputs: dual queued analog-to-digital converters (QADC64)
Submicron HCMOS (CDR1) technology
272-pin plastic ball grid array (PBGA) packaging
40-MHz operation, -40
°C to 125 °C with dual supply (3.3 V, 5 V) (-55 °C to 125 °C
for the suffix A device)
32-bit architecture (PowerPC ISA architecture compliant)
Core performance measured at 52.7-Kbyte Dhrystones (v2.1) @ 40 MHz
Fully static, low power operation
Integrated double-precision floating-point unit
Precise exception model
Table 1. MPC555 Features
Device
Flash
Code Compression
MPC555
448 Kbytes
Code compression not supported
Product Brief
MPC555PB/D
Rev. 3, 2/2003
MPC555 Product Brief
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Freescale Semiconductor, Inc., 2004. All rights reserved.
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