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參數(shù)資料
| 型號： | MPC555 |
| 廠商： | Motorola, Inc. |
| 元件分類： | 32位微控制器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 高度集成，低功耗，32位微控制器 |
| 文件頁數(shù)： | 24/32頁 |
| 文件大?。?/td> | 219K |
| 代理商： | MPC555 |
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Application Note
AN1778
24
MOTOROLA
Table 7. MDASMSCR Bit Settings
Bit(s)
0
Name
PIN
Description
Pin input status. The pin input status bit reflects the status of the corresponding pin.
Wired-OR. In the DIS, IPWM, IPM, and IC modes, the WOR bit is not used; reading
this bit returns the value that was previously written. In the OCB, OCAB, and OPWM
modes, the WOR bit selects whether the output buffer is configured for open-drain or
totem pole operation.
0 = Output buffer is totem pole.
1 = Output buffer is open-drain.
Freeze enable. This active high read/write control bit enables the MDASM to
recognize the MIOB freeze signal.
0 = The MDASM is not frozen even if the MIOB freeze line is active.
1 = The MDASM is frozen if the MIOB freeze line is active.
0
Polarity. In DIS mode, this bit is not used; reading it returns the last value written.
In IPWM mode, this bit is used to select the capture edge sensitivity of channels A
and B.
0 = Channel A captures on a rising edge. Channel B captures on a falling edge.
1 = Channel A captures on a falling edge. Channel B captures on a rising edge.
In IPM and IC modes, the EDPOL bit is used to select the input capture edge
sensitivity of channel A.
0 = Channel A captures on a rising edge.
1 = Channel A captures on a falling edge.
In OCB, OCAB, and OPWM modes, the EDPOL bit is used to select the voltage level
on the output pin.
0 = The output flip-flop logic level appears on the output pin: A compare on channel A
sets the output pin; a compare on channel B resets the output pin.
1 = The complement of the output flip-flop logic level appears on the output pin: A
compare on channel A resets output pin; a compare on channel B sets output pin.
Force A. In OCB, OCAB, and OPWM modes, the FORCA bit allows the software to
force the output flip-flop to behave as if a successful comparison had occurred on
channel A (except that the FLAG line is not activated). Writing a 1 to FORCA sets
the output flip-flop; writing a 0 to it has no effect.
In DIS, IPWM, IPM, & IC modes, the FORCA bit is not used; writing to it has no effect.
FORCA is cleared by reset and is always read as 0. Writing a 1 to both FORCA and
FORCB simultaneously resets the output flip-flop.
Force B. In OCB, OCAB, and OPWM modes, the FORCB bit allows the software to
force the output flip-flop to behave as if a successful comparison had occurred on
channel B (except that the FLAG line is not activated). Writing a 1 to FORCB resets
the output flip-flop; writing a 0 to it has no effect.
In DIS, IPWM, IPM, & IC modes, the FORCB bit is not used; writing to it has no effect.
FORCB is cleared by reset and is always read as 0. Writing a 1 to both FORCA and
FORCB simultaneously resets the output flip-flop.
Reserved
Bus select.These bits are used to select which of the four possible 16-bit counter
buses passing nearby is used by the MDASM.
0
Mode select. These four mode select bits select the mode of operation of the MDASM.
To avoid spurious interrupts, it is recommended that MDASM interrupts are disabled
before changing the operating mode. It is also imperative to go through disable
mode before changing the operating mode. See
Table 8
for details.
1
WOR
2
FREN
3
—
4
EDPOL
5
FORCA
6
FORCB
7:8
—
9:10
BSL
11
—
12:15
MOD
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