參數(shù)資料
型號(hào)： MPC5554MZP132R2
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 12/58頁(yè)
文件大?。?/td> 0K
描述： IC MCU 2M FLASH 132MHZ 416-PBGA
產(chǎn)品培訓(xùn)模塊： MPC55xx PitchPak Family
標(biāo)準(zhǔn)包裝： 500
系列： MPC55xx Qorivva
核心處理器： e200z6
芯體尺寸： 32-位
速度： 132MHz
連通性： CAN，EBI/EMI，SCI，SPI
外圍設(shè)備： DMA，POR，PWM，WDT
輸入/輸出數(shù)： 256
程序存儲(chǔ)器容量： 2MB（2M x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 64K x 8
電壓 - 電源 (Vcc/Vdd)： 1.35 V ~ 1.65 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 40x12b
振蕩器型： 外部
工作溫度： -40°C ~ 125°C
封裝/外殼： 416-BBGA
包裝： 帶卷 (TR)
配用： MPC5554INT-ND - BOARD DEMO MPC5554
MPC5554EVBISYS-ND - BOARD EVAL ISYSTEMS MPC5554
MPC5554EVBGHS-ND - BOARD EVAL GREEN HILLS SOFTWARE
MPC5554EVB-ND - BOARD EVALUATION MPC5554
MPC5534EVBISYS-ND - KIT EVAL ISYSTEMS MPC5534
MPC5534EVBGHS-ND - KIT EVAL GREEN HILLS SOFTWARE
MPC5534EVB-ND - KIT EVALUATION MPC5534MZP80
MPC5554EVBE-ND - BOARD EVAL FOR MPC5554
MPC5534EVBE-ND - BOARD EVAL FOR MPC5534
MPC5554 Microcontroller Data Sheet, Rev. 4
Overview
Freescale Semiconductor
2
The MPC5500 family of parts contains many new features coupled with high performance CMOS
technology to provide significant performance improvement over the MPC565.
The MPC5554 has two levels of memory hierarchy. The fastest accesses are to the 32-kilobytes (KB)
unified cache. The next level in the hierarchy contains the 64-KB on-chip internal SRAM and
two-megabytes (MB) internal flash memory. The internal SRAM and flash memory hold instructions and
data. The external bus interface is designed to support most of the standard memories used with the
MPC5xx family.
The complex input/output timer functions of the MPC5554 are performed by two enhanced time processor
unit (eTPU) engines. Each eTPU engine controls 32 hardware channels, providing a total of 64 hardware
channels. The eTPU has been enhanced over the TPU by providing: 24-bit timers, double-action hardware
channels, variable number of parameters per channel, angle clock hardware, and additional control and
arithmetic instructions. The eTPU is programmed using a high-level programming language.
The less complex timer functions of the MPC5554 are performed by the enhanced modular input/output
system (eMIOS). The eMIOS’ 24 hardware channels are capable of single-action, double-action,
pulse-width modulation (PWM), and modulus-counter operations. Motor control capabilities include
edge-aligned and center-aligned PWM.
Off-chip communication is performed by a suite of serial protocols including controller area networks
(FlexCANs), enhanced deserial/serial peripheral interfaces (DSPIs), and enhanced serial communications
interfaces (eSCIs). The DSPIs support pin reduction through hardware serialization and deserialization of
timer channels and general-purpose input/output (GPIOs) signals.
The MCU has an on-chip enhanced queued dual analog-to-digital converter (eQADC). 324 s40-channels.
The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration
and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset
control are also determined by the SIU. The internal multiplexer submodule provides multiplexing of
eQADC trigger sources, daisy chaining the DSPIs, and external interrupt signal multiplexing.
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MPC555D 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:This document provides an overview of the MPC555 microcontroller, including a block diagram showing the major modular components and sections that lis
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