Input Value of Pins During POR" />
參數(shù)資料
型號(hào)： MPC5554EVBGHS
廠(chǎng)商： Freescale Semiconductor
文件頁(yè)數(shù)： 5/58頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL GREEN HILLS SOFTWARE
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 微控制器
適用于相關(guān)產(chǎn)品： MPC5554
所含物品： 評(píng)估板和演示軟件
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Electrical Characteristics
MPC5554 Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
13
3.7.1
Input Value of Pins During POR Dependent on VDD33
When powering up the device, VDD33 must not lag the latest VDDSYN or RESET power pin (VDDEH6) by
more than the VDD33 lag specification listed in Table 6, spec 8. This avoids accidentally selecting the
bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and
therefore cannot read the default state when POR negates. VDD33 can lag VDDSYN or the RESET power
pin (VDDEH6), but cannot lag both by more than the VDD33 lag specification. This VDD33 lag specification
applies during power up only. VDD33 has no lead or lag requirements when powering down.
3.7.2
Power-Up Sequence (VRC33 Grounded)
The 1.5 V VDD power supply must rise to 1.35 V before the 3.3 V VDDSYN power supply and the RESET
power supply rises above 2.0 V. This ensures that digital logic in the PLL for the 1.5 V power supply does
not begin to operate below the specified operation range lower limit of 1.35 V. Because the internal 1.5 V
POR is disabled, the internal 3.3 V POR or the RESET power POR must hold the device in reset. Since
they can negate as low as 2.0 V, VDD must be within specification before the 3.3 V POR and the RESET
POR negate.
Figure 3. Power-Up Sequence (VRC33 Grounded)
3.7.3
Power-Down Sequence (VRC33 Grounded)
The only requirement for the power-down sequence with VRC33 grounded is if VDD decreases to less than
its operating range, VDDSYN or the RESET power must decrease to less than 2.0 V before the VDD power
increases to its operating range. This ensures that the digital 1.5 V logic, which is reset only by an ORed
POR and can cause the 1.5 V supply to decrease less than its specification value, resets correctly. See
Table 6, footnote 1.
VDDSYN and RESET Power
VDD
2.0 V
1.35 V
VDD must reach 1.35 V before VDDSYN and the RESET power reach 2.0 V
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC5554EVBISYS 功能描述:開(kāi)發(fā)軟件 ISYSTEMS CONTENT Qorivva RoHS:否 制造商:Atollic Inc. 產(chǎn)品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
MPC5554FS 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Qorivva MPC5554 Family
MPC5554INT 功能描述:開(kāi)發(fā)板和工具包 - 其他處理器 MPC5554 CUST. DEMO Qorivva RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類(lèi)型:I2C, SPI, USB 工作電源電壓:
MPC5554MVR112 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Microcontroller
MPC5554MVR132 功能描述:32位微控制器 - MCU MPC5554 COPPERHEAD Qorivva RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線(xiàn)寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT
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