參數(shù)資料
型號(hào)： MPC5554EVBE
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 52/58頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR MPC5554
產(chǎn)品培訓(xùn)模塊： MPC55xx PitchPak Family
標(biāo)準(zhǔn)包裝： 1
系列： Qorivva
類型： MCU
適用于相關(guān)產(chǎn)品： MPC5554
所含物品： 評(píng)估板和演示軟件
配用： MFR4310FRDC-ND - FRDC FLEXRAY DAUGHTER CARD
相關(guān)產(chǎn)品： MPC5554MZP132R2-ND - IC MCU 2M FLASH 132MHZ 416-PBGA
MPC5554MZP132-ND - IC MCU 2M FLASH 132MHZ 416-PBGA
MPC5554MVR132R2-ND - IC MCU 2M FLASH 132MHZ 416-PBGA
MPC5554MVR132-ND - IC MCU 2M FLASH 132MHZ 416-PBGA
MPC5554AZP132-ND - IC MPU 2M FLASH 132MHZ 416-PBGA
MPC5554 Microcontroller Data Sheet, Rev. 4
Revision History for the MPC5554 Data Sheet
Freescale Semiconductor
56
Table 20 (JTAG Pin AC Electrical Characteristics) JTAG Pin AC Electrical Characteristics
Footnote 1: Removed VDD = 1.35–1.65 V, and VDD33 and VDDSYN = 3.0–3.6 V.
External Bus Frequency in the table heading: Added footnote that reads: Speed is the nominal maximum
frequency. Max speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow
for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and 132 MHz parts
allow for 128 MHz system clock + 2% FM.
Specifications 5, 6, 7, and 8: Reordered the EBI signals within each specification.
Specifications 7 and 8: Removed EBI signals BDIP, OE, TSIZ[0:1], WE/BE[0:3].
Footnote 1: Removed VDD = 1.35–1.65 V, and VDD33 and VDDSYN = 3.0–3.6 V.
Footnote 8: Changed EBTS to SIU_ECCR[EBTS].
Table 23 (External Interrupt Timing) External Interrupt Timing (IRQ Signals)
Footnote 1: Removed VDD = 1.35–1.65 V; changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V.
Footnote 1: Changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V.
Footnote 1: Changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V.
Footnote 1, changed ‘VDDEH = 3.0–5.5 V;’ to ‘VDDEH = 3.0–5.25 V;’
Table Title: Added footnote that reads: Speed is the nominal maximum frequency. Max speed is the maximum
speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM;
114 MHz parts allow for 112 MHz system clock + 2% FM; and 132 MHz parts allow for
128 MHz system clock + 2% FM.
Spec 1: SCK cycle time; Changed to 80 MHz minimum column from 25 to 24.4; 112 MHz minimum column from
17.9 to 17.5; 112 MHz maximum column from 2.0 to 2.1.
Table 27 (EQADC SSI Timing Characteristics) EQADC SSI Timing Characteristics
Footnote 1: Changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V.
Table 28. Changes Between Rev. 2.0 and 3.0 (continued)
Location
Description of Changes
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC5554EVBE 制造商:Freescale Semiconductor 功能描述:MPC5554 CUSTOMER DEMO BD
MPC5554EVBGHS 功能描述:開(kāi)發(fā)軟件 GREEN HILLS SW Qorivva RoHS:否 制造商:Atollic Inc. 產(chǎn)品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
MPC5554EVBISYS 功能描述:開(kāi)發(fā)軟件 ISYSTEMS CONTENT Qorivva RoHS:否 制造商:Atollic Inc. 產(chǎn)品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
MPC5554FS 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Qorivva MPC5554 Family
MPC5554INT 功能描述:開(kāi)發(fā)板和工具包 - 其他處理器 MPC5554 CUST. DEMO Qorivva RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
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