參數(shù)資料
型號: MPC5553MZQ132
廠商: Freescale Semiconductor
文件頁數(shù): 29/68頁
文件大小: 0K
描述: IC MCU MPC5553 REV A 324-PBGA
產(chǎn)品培訓模塊: MPC55xx PitchPak Family
標準包裝: 60
系列: MPC55xx Qorivva
核心處理器: e200z6
芯體尺寸: 32-位
速度: 132MHz
連通性: CAN,EBI/EMI,以太網(wǎng),SCI,SPI
外圍設備: DMA,POR,PWM,WDT
輸入/輸出數(shù): 220
程序存儲器容量: 1.5MB(1.5M x 8)
程序存儲器類型: 閃存
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.35 V ~ 1.65 V
數(shù)據(jù)轉換器: A/D 40x12b
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 324-BBGA
包裝: 托盤
配用: MPC5553EVBISYS-ND - KIT EVAL ISYSTEMS MPC5553
MPC5553EVBGHS-ND - KIT EVAL GREEN HILLS SOFTWARE
MPC5553EVB-ND - KIT EVAL MPC5553MZP132
MPC5553EVBE-ND - BOARD EVAL FOR MPC5553
Electrical Characteristics
MPC5553 Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
35
6a
CLKOUT positive edge to output
signal valid (output delay)
Calibration bus interface
CAL_CS[0, 2:3]
CAL_ADDR[10:11, 27:30]
CAL_DATA[0:15]
CAL_WE/BE[0:1]
tCCOV
11.08
12.0
9.5
8.0
ns
EBTS = 0
EBTS = 1
Output valid time
selectable via
SIU_ECCR
[EBTS] bit.
7
Input signal valid to CLKOUT
positive edge (setup time)
External bus interface
ADDR[8:31]
DATA[0:31] 5
RD_WR
TA
TEA 6
TS
tCIS
10.0
7.0
5.0
ns
Input signal valid to CLKOUT
positive edge (setup time)
Calibration bus interface
CAL_ADDR[10:11, 27:30]
CAL_DATA[0:15]
tCCIS
11.0
8.0
6.0
ns
8
CLKOUT positive edge to input
signal invalid (hold time)
External bus interface
ADDR[8:31]
DATA[0:31] 5
RD_WR
TA
TEA 6
TS
tCIH
1.0
1.0
1.0
ns
CLKOUT positive edge to input
signal invalid (hold time)
Calibration bus interface
CAL_ADDR[10:11, 27:30]
CAL_DATA[0:15]
tCCIH
1.0
1.0
1.0
ns
1 EBI timing specified at: V
DDE = 1.6–3.6 V (unless stated otherwise); TA = TL to TH; and CL = 30 pF with DSC = 0b10.
2 Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed including frequency modulation (FM).
82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and
132 MHz parts allow for 128 MHz system clock + 2% FM.
3 The external bus is limited to half the speed of the internal bus.
4 Refer to fast pad timing in Table 17 and Table 18 (different values for 1.8 V and 3.3 V).
5 Due to pin limitations, the DATA[16:31] signals are not available on the 324 package.
Table 22. Bus Operation Timing1 (continued)
Spec
Characteristic
and
Description
Symbol
External Bus Frequency 2, 3
Unit
Notes
40 MHz
56 MHz
66 MHz
Min.
Max.
Min.
Max.
Min.
Max.
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